@samitouri / QOSamiQemu / commits / 6a71b3b5ec

Hexagon (target/hexagon) Disassembly of invalid packets

We pass the Hexagon CPU definition to disassemble_hexagon. This allows decode_packet to know if the opcodes are supported. Note that we print valid instructions in a packet when one or more is invalid. Rather than this 0x0002128c: 0x1eae4fec { <invalid> 0x00021290: 0x1c434c04 <invalid> 0x00021294: 0x1e03edf0 <invalid> } We print this 0x0002128c: 0x1eae4fec { <invalid> 0x00021290: 0x1c434c04 V4.w = vadd(V12.w,V3.w) 0x00021294: 0x1e03edf0 V16 = V13 } Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Taylor Simpson committed Feb 17, 2026 at 14:22 UTC 6a71b3b5ec23394f209b968478f401189b3e9132
6 files changed +37 -9
disas/hexagon.c
+2 -1
@@ -31,6 +31,7 @@
31
32 int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
33 {
34 + const HexagonCPUDef *hex_def = (const HexagonCPUDef *)info->target_info;
35 uint32_t words[PACKET_WORDS_MAX];
36 bool found_end = false;
37 GString *buf;
@@ -58,7 +59,7 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
59 }
60
61 buf = g_string_sized_new(PACKET_BUFFER_LEN);
61 - len = disassemble_hexagon(words, i, memaddr, buf);
62 + len = disassemble_hexagon(words, i, memaddr, buf, hex_def);
63 (*info->fprintf_func)(info->stream, "%s", buf->str);
64 g_string_free(buf, true);
65
target/hexagon/cpu.c
+2
@@ -297,8 +297,10 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
297 static void hexagon_cpu_disas_set_info(const CPUState *cs,
298 disassemble_info *info)
299 {
300 + const HexagonCPU *cpu = HEXAGON_CPU(cs);
301 info->print_insn = print_insn_hexagon;
302 info->endian = BFD_ENDIAN_LITTLE;
303 + info->target_info = HEXAGON_CPU_GET_CLASS(cpu)->hex_def;
304 }
305
306 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
target/hexagon/cpu_bits.h
+3 -1
@@ -19,6 +19,7 @@
19 #define HEXAGON_CPU_BITS_H
20
21 #include "qemu/bitops.h"
22 +#include "cpu-qom.h"
23
24 #define PCALIGN 4
25 #define PCALIGN_MASK (PCALIGN - 1)
@@ -65,6 +66,7 @@ static inline bool is_packet_end(uint32_t endocing)
66 return ((bits == 0x3) || (bits == 0x0));
67 }
68
68 -int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf);
69 +int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf,
70 + const HexagonCPUDef *hex_def);
71
72 #endif
target/hexagon/decode.c
+21 -4
@@ -828,19 +828,36 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
828
829 /* Used for "-d in_asm" logging */
830 int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
831 - GString *buf)
831 + GString *buf, const HexagonCPUDef *hex_def)
832 {
833 + HexagonCPUDef any_def = {
834 + .hex_version = HEX_VER_ANY, /* Allow decode to accept anything */
835 + };
836 DisasContext ctx;
837 Packet pkt;
838
839 memset(&ctx, 0, sizeof(DisasContext));
840 + ctx.hex_def = &any_def;
841 ctx.pkt = &pkt;
842
843 if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {
840 - snprint_a_pkt_disas(buf, &pkt, words, pc);
844 + snprint_a_pkt_disas(buf, &pkt, words, pc, hex_def);
845 return pkt.encod_pkt_size_in_bytes;
846 } else {
843 - g_string_assign(buf, "<invalid>");
844 - return 0;
847 + for (int i = 0; i < nwords; i++) {
848 + g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]);
849 + if (i == 0) {
850 + g_string_append(buf, "{");
851 + }
852 + g_string_append(buf, "\t");
853 + g_string_append(buf, "<invalid>");
854 + if (i < nwords - 1) {
855 + pc += 4;
856 + g_string_append_printf(buf, "\n0x" TARGET_FMT_lx ": ",
857 + (target_ulong)pc);
858 + }
859 + }
860 + g_string_append(buf, " }");
861 + return nwords * sizeof(uint32_t);
862 }
863 }
target/hexagon/printinsn.c
+7 -2
@@ -21,6 +21,7 @@
21 #include "insn.h"
22 #include "reg_fields.h"
23 #include "internal.h"
24 +#include "decode.h"
25
26 static const char *sreg2str(unsigned int reg)
27 {
@@ -51,7 +52,7 @@ static void snprintinsn(GString *buf, Insn *insn)
52 }
53
54 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
54 - target_ulong pc)
55 + target_ulong pc, const HexagonCPUDef *hex_def)
56 {
57 bool has_endloop0 = false;
58 bool has_endloop1 = false;
@@ -83,7 +84,11 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
84 }
85
86 g_string_append(buf, "\t");
86 - snprintinsn(buf, &(pkt->insn[i]));
87 + if (opcode_supported(pkt->insn[i].opcode, hex_def)) {
88 + snprintinsn(buf, &(pkt->insn[i]));
89 + } else {
90 + g_string_append(buf, "<invalid>");
91 + }
92
93 if (i < pkt->num_insns - 1) {
94 /*
target/hexagon/printinsn.h
+2 -1
@@ -18,10 +18,11 @@
18 #ifndef HEXAGON_PRINTINSN_H
19 #define HEXAGON_PRINTINSN_H
20
21 +#include "cpu-qom.h"
22 #include "insn.h"
23
24 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
24 - target_ulong pc);
25 + target_ulong pc, const HexagonCPUDef *hex_def);
26 void snprint_a_pkt_debug(GString *buf, Packet *pkt);
27
28 #endif