target/riscv: Remove MTTCG check for x-rv128 CPU model
We had to check that mttcg was not used when executing QEMU with -cpu x-rv128 as a single 128-bit access was done as two distinct 64-bit accesses. Now that we use the 128-bit ld/st that access the data atomically, this check is no longer necessary. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260318103122.97244-5-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot committed
Mar 18, 2026 at 11:31 UTC
717bf920cbf078a32415a107b0e2a20a5f3d2007
1 file changed
-10
target/riscv/tcg/tcg-cpu.c
-10
@@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
1305
}
1306
1307
#ifndef CONFIG_USER_ONLY
1308
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
1309
-
1310
- if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
1311
- /* Missing 128-bit aligned atomics */
1312
- error_setg(errp,
1313
- "128-bit RISC-V currently does not work with Multi "
1314
- "Threaded TCG. Please use: -accel tcg,thread=single");
1315
- return false;
1316
- }
1317
-
1308
CPURISCVState *env = &cpu->env;
1309
1310
tcg_cflags_set(CPU(cs), CF_PCREL);