target/mips: Reduce CPUState scope when used with CPU_FOREACH()
When possible, reduce CPUState variable scope. Prefer cpu_env(cpu) over &cpu->env. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Message-Id: <20260415215539.92629-8-philmd@linaro.org>
Philippe Mathieu-Daudé committed
May 6, 2026 at 14:37 UTC
734bd8303027cfc566c9507b08ceff9d3bc2cd71
3 files changed
+25
-21
target/mips/internal.h
+6
-5
@@ -280,7 +280,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
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static inline int mips_vp_active(CPUMIPSState *env)
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{
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- CPUState *other_cs = first_cpu;
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+ CPUState *cs = first_cpu;
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/* Check if the VP disabled other VPs (which means the VP is enabled) */
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
@@ -288,10 +288,11 @@ static inline int mips_vp_active(CPUMIPSState *env)
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}
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/* Check if the virtual processor is disabled due to a DVP */
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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- if ((&other_cpu->env != env) &&
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- ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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+ CPU_FOREACH(cs) {
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+ CPUMIPSState *other_env = cpu_env(cs);
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+
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+ if ((other_env != env) &&
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+ ((other_env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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return 0;
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}
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}
target/mips/tcg/system/cp0_helper.c
+16
-12
@@ -1566,13 +1566,14 @@ target_ulong helper_emt(void)
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target_ulong helper_dvpe(CPUMIPSState *env)
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{
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- CPUState *other_cs = first_cpu;
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MIPSCPU *cpu = env_archcpu(env);
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target_ulong prev = cpu->mvp->CP0_MVPControl;
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if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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+ CPUState *cs = first_cpu;
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+
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+ CPU_FOREACH(cs) {
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+ MIPSCPU *other_cpu = MIPS_CPU(cs);
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/* Turn off all VPEs except the one executing the dvpe. */
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if (&other_cpu->env != env) {
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other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
@@ -1585,13 +1586,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
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target_ulong helper_evpe(CPUMIPSState *env)
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{
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- CPUState *other_cs = first_cpu;
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MIPSCPU *cpu = env_archcpu(env);
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target_ulong prev = cpu->mvp->CP0_MVPControl;
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if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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+ CPUState *cs = first_cpu;
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+
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+ CPU_FOREACH(cs) {
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+ MIPSCPU *other_cpu = MIPS_CPU(cs);
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if (&other_cpu->env != env
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/* If the VPE is WFI, don't disturb its sleep. */
@@ -1608,12 +1610,13 @@ target_ulong helper_evpe(CPUMIPSState *env)
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/* R6 Multi-threading */
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target_ulong helper_dvp(CPUMIPSState *env)
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{
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- CPUState *other_cs = first_cpu;
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target_ulong prev = env->CP0_VPControl;
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if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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+ CPUState *cpu = first_cpu;
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+
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+ CPU_FOREACH(cpu) {
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+ MIPSCPU *other_cpu = MIPS_CPU(cpu);
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/* Turn off all VPs except the one executing the dvp. */
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if (&other_cpu->env != env) {
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mips_vpe_sleep(other_cpu);
@@ -1626,12 +1629,13 @@ target_ulong helper_dvp(CPUMIPSState *env)
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target_ulong helper_evp(CPUMIPSState *env)
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{
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- CPUState *other_cs = first_cpu;
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target_ulong prev = env->CP0_VPControl;
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if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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+ CPUState *cpu = first_cpu;
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+
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+ CPU_FOREACH(cpu) {
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+ MIPSCPU *other_cpu = MIPS_CPU(cpu);
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if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
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/*
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* If the VP is WFI, don't disturb its sleep.
target/mips/tcg/system/tlb_helper.c
+3
-4
@@ -346,15 +346,14 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
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uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
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uint8_t invMsgR = 0;
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uint32_t invMsgMMid = env->CP0_MemoryMapID;
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- CPUState *other_cs = first_cpu;
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+ CPUState *cpu = first_cpu;
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#ifdef TARGET_MIPS64
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invMsgR = extract64(arg, 62, 2);
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#endif
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- CPU_FOREACH(other_cs) {
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- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
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- global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,
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+ CPU_FOREACH(cpu) {
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+ global_invalidate_tlb(cpu_env(cpu), invMsgVPN2, invMsgR, invMsgMMid,
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invAll, invVAMMid, invMMid, invVA);
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}
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}