hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1
The IRS_CR0 register has the main enable bit for the IRS, and an IDLE bit to tell the guest when an enable/disable transition has completed. The IRS_CR1 register has cacheability, shareability and cache hint information to use for IRS memory accesses; since QEMU doesn't care about this we can make it simply reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-30-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
75ded6e07a2009581035551dd793a25e0c70291c
3 files changed
+17
hw/intc/arm_gicv5.c
+13
@@ -1080,6 +1080,13 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
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}
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*data = v;
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return true;
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+ case A_IRS_CR0:
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+ /* Enabling is instantaneous for us so IDLE is always 1 */
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+ *data = cs->irs_cr0[domain] | R_IRS_CR0_IDLE_MASK;
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+ return true;
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+ case A_IRS_CR1:
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+ *data = cs->irs_cr1[domain];
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+ return true;
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}
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return false;
@@ -1159,6 +1166,12 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,
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trace_gicv5_spi_state(id, spi->level, spi->pending, spi->active);
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return true;
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}
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+ case A_IRS_CR0:
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+ cs->irs_cr0[domain] = data & R_IRS_CR0_IRSEN_MASK;
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+ return true;
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+ case A_IRS_CR1:
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+ cs->irs_cr1[domain] = data;
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+ return true;
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}
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return false;
hw/intc/arm_gicv5_common.c
+2
@@ -64,6 +64,8 @@ static void gicv5_common_reset_hold(Object *obj, ResetType type)
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memset(cs->irs_ist_baser, 0, sizeof(cs->irs_ist_baser));
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memset(cs->irs_ist_cfgr, 0, sizeof(cs->irs_ist_cfgr));
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+ memset(cs->irs_cr0, 0, sizeof(cs->irs_cr0));
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+ memset(cs->irs_cr1, 0, sizeof(cs->irs_cr1));
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if (cs->spi) {
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GICv5Domain mp_domain;
include/hw/intc/arm_gicv5_common.h
+2
@@ -86,6 +86,8 @@ struct GICv5Common {
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uint64_t irs_ist_baser[NUM_GICV5_DOMAINS];
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uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS];
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uint32_t irs_spi_selr[NUM_GICV5_DOMAINS];
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+ uint32_t irs_cr0[NUM_GICV5_DOMAINS];
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+ uint32_t irs_cr1[NUM_GICV5_DOMAINS];
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/*
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* Pointer to an array of state information for the SPIs. Array