hw/intc/arm_gicv5: Cache LPI IST config in a struct
The IRS has multiple ISTs, for different contexts: * physical LPIs (separately for each interrupt domain) * virtual LPIs * virtual SPIs The config information for physical LPIs is in the IRS_IST_BASER and IRS_IST_CFGR registers; for virtual LPIs and virtual SPIs it will be in the L2_VMTE VM table entry. We would like to be able to write generic code that can manipulate any of these ISTs. Define a struct which captures the config information for an IST, and cache the IRS_IST_CFGR/IRS_IST_BASER data into this format when the guest sets the VALID bit. This also allows us to enforce the correct handling of reserved and out-of-range values, and expand the encodings of sizes into a more convenient format for later use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-18-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
78919a66ae549683831bcde8330dc7c083440edb
3 files changed
+78
hw/intc/arm_gicv5.c
+64
@@ -278,9 +278,68 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)
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}
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cs->irs_ist_baser[domain] = FIELD_DP64(cs->irs_ist_baser[domain],
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IRS_IST_BASER, VALID, valid);
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+ s->phys_lpi_config[domain].valid = false;
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+ trace_gicv5_ist_invalid(domain_name[domain]);
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return;
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}
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cs->irs_ist_baser[domain] = value;
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+
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+ if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {
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+ /*
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+ * If the guest just set VALID then capture data into config struct,
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+ * sanitize the reserved values, and expand fields out into byte counts.
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+ */
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+ GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];
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+ uint8_t istbits, l2bits, l2_idx_bits;
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+ uint8_t id_bits = FIELD_EX64(cs->irs_ist_cfgr[domain],
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+ IRS_IST_CFGR, LPI_ID_BITS);
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+ id_bits = MIN(MAX(id_bits, QEMU_GICV5_MIN_LPI_ID_BITS), QEMU_GICV5_ID_BITS);
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+
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+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, ISTSZ)) {
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+ case 0:
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+ case 3: /* reserved: acts like the minimum required size */
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+ istbits = 2;
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+ break;
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+ case 1:
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+ istbits = 3;
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+ break;
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+ case 2:
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+ istbits = 4;
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+ break;
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+ default:
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+ g_assert_not_reached();
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+ }
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+ switch (FIELD_EX64(cs->irs_ist_cfgr[domain], IRS_IST_CFGR, L2SZ)) {
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+ case 0:
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+ case 3: /* reserved; CONSTRAINED UNPREDICTABLE */
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+ l2bits = 12; /* 4K: 12 bits */
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+ break;
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+ case 1:
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+ l2bits = 14; /* 16K: 14 bits */
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+ break;
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+ case 2:
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+ l2bits = 16; /* 64K: 16 bits */
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+ break;
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+ default:
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+ g_assert_not_reached();
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+ }
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+ /*
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+ * Calculate how many bits of an ID index the L2 table
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+ * (e.g. if we need 14 bits to index each byte in a 16K L2 table,
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+ * but each entry is 4 bytes wide then we need 14 - 2 = 12 bits
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+ * to index an entry in the table).
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+ */
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+ l2_idx_bits = l2bits - istbits;
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+ cfg->base = cs->irs_ist_baser[domain] & R_IRS_IST_BASER_ADDR_MASK;
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+ cfg->id_bits = id_bits;
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+ cfg->istsz = 1 << istbits;
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+ cfg->l2_idx_bits = l2_idx_bits;
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+ cfg->structure = FIELD_EX64(cs->irs_ist_cfgr[domain],
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+ IRS_IST_CFGR, STRUCTURE);
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+ cfg->valid = true;
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+ trace_gicv5_ist_valid(domain_name[domain], cfg->base, cfg->id_bits,
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+ cfg->l2_idx_bits, cfg->istsz, cfg->structure);
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+ }
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}
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static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
@@ -553,6 +612,11 @@ static void gicv5_reset_hold(Object *obj, ResetType type)
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if (c->parent_phases.hold) {
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c->parent_phases.hold(obj, type);
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}
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+
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+ /* IRS_IST_BASER and IRS_IST_CFGR reset to 0, clear cached info */
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+ for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {
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+ s->phys_lpi_config[i].valid = false;
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+ }
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}
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static void gicv5_set_idregs(GICv5Common *cs)
hw/intc/trace-events
+2
@@ -233,6 +233,8 @@ gicv5_badread(const char *domain, uint64_t offset, unsigned size) "GICv5 IRS %s
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gicv5_write(const char *domain, uint64_t offset, uint64_t data, unsigned size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
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gicv5_badwrite(const char *domain, uint64_t offset, uint64_t data, unsigned size) "GICv5 IRS %s config frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error"
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gicv5_spi(uint32_t id, int level) "GICv5 SPI ID %u asserted at level %d"
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+gicv5_ist_valid(const char *domain, uint64_t base, uint8_t id_bits, uint8_t l2_idx_bits, uint8_t istsz, bool structure) "GICv5 IRS %s IST now valid: base 0x%" PRIx64 " id_bits %u l2_idx_bits %u IST entry size %u 2-level %d"
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+gicv5_ist_invalid(const char *domain) "GICv5 IRS %s IST no longer valid"
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# arm_gicv5_common.c
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gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u"
include/hw/intc/arm_gicv5.h
+12
@@ -17,11 +17,23 @@
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OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5)
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+typedef struct GICv5ISTConfig {
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+ hwaddr base; /* Base address */
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+ uint8_t id_bits; /* number of bits in an ID for this table */
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+ uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */
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+ uint8_t istsz; /* L2 ISTE size in bytes */
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+ bool structure; /* true if using 2-level table */
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+ bool valid; /* true if this table is valid and usable */
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+} GICv5ISTConfig;
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+
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/*
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* This class is for TCG-specific state for the GICv5.
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*/
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struct GICv5 {
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GICv5Common parent_obj;
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+
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+ /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */
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+ GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS];
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};
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struct GICv5Class {