target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
Following commit 73ae67fd4e6, extract the implicit MO_TE definition in order to replace it. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/riscv); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260318103122.97244-6-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
Mar 18, 2026 at 11:31 UTC
78dc8c8253e4e54d5f49ef19243431ccc61d68c4
3 files changed
+16
-16
target/riscv/insn_trans/trans_rvzalasr.c.inc
+6
-6
@@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
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static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
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{
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REQUIRE_ZALASR(ctx);
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- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));
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+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
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}
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static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
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{
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REQUIRE_ZALASR(ctx);
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- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));
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+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
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}
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static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_ZALASR(ctx);
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- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));
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+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
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}
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static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
@@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
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static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
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{
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REQUIRE_ZALASR(ctx);
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- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));
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+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
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}
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static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
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{
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REQUIRE_ZALASR(ctx);
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- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));
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+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
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}
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static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_ZALASR(ctx);
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- return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));
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+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
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}
target/riscv/insn_trans/trans_xmips.c.inc
+8
-8
@@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_tl(addr, src, a->imm_y);
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- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);
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+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);
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gen_set_gpr(ctx, a->rd, dest0);
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tcg_gen_addi_tl(addr, addr, 8);
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- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);
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+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);
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gen_set_gpr(ctx, a->rs3, dest1);
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return true;
@@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_tl(addr, src, a->imm_x);
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- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);
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+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);
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gen_set_gpr(ctx, a->rd, dest0);
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tcg_gen_addi_tl(addr, addr, 4);
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- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);
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+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);
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gen_set_gpr(ctx, a->rs3, dest1);
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return true;
@@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_tl(addr, src, a->imm_w);
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- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);
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+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);
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tcg_gen_addi_tl(addr, addr, 8);
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- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);
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+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);
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return true;
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}
@@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_tl(addr, src, a->imm_v);
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- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);
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+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);
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tcg_gen_addi_tl(addr, addr, 4);
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- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);
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+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);
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return true;
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}
target/riscv/insn_trans/trans_zilsd.c.inc
+2
-2
@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
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TCGv addr = get_address(ctx, a->rs1, a->imm);
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TCGv_i64 tmp = tcg_temp_new_i64();
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- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
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+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
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if (a->rd == 0) {
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return true;
@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
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} else {
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tcg_gen_concat_tl_i64(tmp, data_low, data_high);
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}
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- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ);
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+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);
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return true;
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}