target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config
Implement the GIC CDDIS, GIC CDEN, GIC CDAFF, GIC CDPEND and GIC CDHM system instructions. These are all simple wrappers around the equivalent gicv5_set_* functions, like GIC CDPRI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-23-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
7bec1d4428d2a9f439b129b5e8d9244b577dee58
1 file changed
+108
target/arm/tcg/gicv5-cpuif.c
+108
@@ -16,6 +16,25 @@ FIELD(GIC_CDPRI, ID, 0, 24)
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FIELD(GIC_CDPRI, TYPE, 29, 3)
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FIELD(GIC_CDPRI, PRIORITY, 35, 5)
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+FIELD(GIC_CDDIS, ID, 0, 24)
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+FIELD(GIC_CDDIS, TYPE, 29, 3)
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+
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+FIELD(GIC_CDEN, ID, 0, 24)
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+FIELD(GIC_CDEN, TYPE, 29, 3)
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+
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+FIELD(GIC_CDAFF, ID, 0, 24)
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+FIELD(GIC_CDAFF, IRM, 28, 1)
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+FIELD(GIC_CDAFF, TYPE, 29, 3)
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+FIELD(GIC_CDAFF, IAFFID, 32, 16)
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+
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+FIELD(GIC_CDPEND, ID, 0, 24)
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+FIELD(GIC_CDPEND, TYPE, 29, 3)
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+FIELD(GIC_CDPEND, PENDING, 32, 1)
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+
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+FIELD(GIC_CDHM, ID, 0, 24)
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+FIELD(GIC_CDHM, TYPE, 29, 3)
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+FIELD(GIC_CDHM, HM, 32, 1)
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+
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static GICv5Common *gicv5_get_gic(CPUARMState *env)
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{
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return env->gicv5state;
@@ -51,6 +70,30 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)
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return gicv5_logical_domain(env);
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}
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+static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ GICv5IntType type = FIELD_EX64(value, GIC_CDDIS, TYPE);
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+ uint32_t id = FIELD_EX64(value, GIC_CDDIS, ID);
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+ bool virtual = false;
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+ GICv5Domain domain = gicv5_current_phys_domain(env);
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+
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+ gicv5_set_enabled(gic, id, false, domain, type, virtual);
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+}
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+
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+static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ GICv5IntType type = FIELD_EX64(value, GIC_CDEN, TYPE);
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+ uint32_t id = FIELD_EX64(value, GIC_CDEN, ID);
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+ bool virtual = false;
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+ GICv5Domain domain = gicv5_current_phys_domain(env);
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+
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+ gicv5_set_enabled(gic, id, true, domain, type, virtual);
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+}
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+
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static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
@@ -64,6 +107,46 @@ static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri,
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gicv5_set_priority(gic, id, priority, domain, type, virtual);
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}
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+static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ uint32_t iaffid = FIELD_EX64(value, GIC_CDAFF, IAFFID);
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+ GICv5RoutingMode irm = FIELD_EX64(value, GIC_CDAFF, IRM);
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+ GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE);
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+ uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID);
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+ bool virtual = false;
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+ GICv5Domain domain = gicv5_current_phys_domain(env);
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+
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+ gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual);
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+}
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+
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+static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ bool pending = FIELD_EX64(value, GIC_CDPEND, PENDING);
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+ GICv5IntType type = FIELD_EX64(value, GIC_CDPEND, TYPE);
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+ uint32_t id = FIELD_EX64(value, GIC_CDPEND, ID);
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+ bool virtual = false;
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+ GICv5Domain domain = gicv5_current_phys_domain(env);
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+
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+ gicv5_set_pending(gic, id, pending, domain, type, virtual);
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+}
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+
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+static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri,
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+ uint64_t value)
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+{
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ GICv5HandlingMode hm = FIELD_EX64(value, GIC_CDHM, HM);
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+ GICv5IntType type = FIELD_EX64(value, GIC_CDAFF, TYPE);
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+ uint32_t id = FIELD_EX64(value, GIC_CDAFF, ID);
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+ bool virtual = false;
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+ GICv5Domain domain = gicv5_current_phys_domain(env);
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+
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+ gicv5_set_handling(gic, id, hm, domain, type, virtual);
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+}
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+
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static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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/*
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* Barrier: wait until the effects of a cpuif system register
@@ -86,11 +169,36 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.opc0 = 1, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NOP,
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},
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+ { .name = "GIC_CDDIS", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
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+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .writefn = gic_cddis_write,
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+ },
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+ { .name = "GIC_CDEN", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
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+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .writefn = gic_cden_write,
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+ },
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{ .name = "GIC_CDPRI", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 2,
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.access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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.writefn = gic_cdpri_write,
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},
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+ { .name = "GIC_CDAFF", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 3,
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+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .writefn = gic_cdaff_write,
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+ },
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+ { .name = "GIC_CDPEND", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 4,
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+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .writefn = gic_cdpend_write,
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+ },
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+ { .name = "GIC_CDHM", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 1, .opc1 = 0, .crn = 12, .crm = 2, .opc2 = 1,
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+ .access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .writefn = gic_cdhm_write,
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+ },
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};
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void define_gicv5_cpuif_regs(ARMCPU *cpu)