target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1
ICC_IDR0_EL1 is an identification register; we can implement this as a simple constant value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-36-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
7c05b9ef753d2b9a91ff0d4b527c4779ed85b0ea
1 file changed
+17
target/arm/tcg/gicv5-cpuif.c
+17
@@ -38,6 +38,18 @@ FIELD(GIC_CDHM, HM, 32, 1)
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FIELD(GIC_CDRCFG, ID, 0, 24)
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FIELD(GIC_CDRCFG, TYPE, 29, 3)
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+FIELD(ICC_IDR0_EL1, ID_BITS, 0, 4)
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+FIELD(ICC_IDR0_EL1, PRI_BITS, 4, 4)
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+FIELD(ICC_IDR0_EL1, GCIE_LEGACY, 8, 4)
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+
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+/*
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+ * We implement 24 bits of interrupt ID, the mandated 5 bits of priority,
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+ * and no legacy GICv3.3 vcpu interface (yet)
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+ */
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+#define QEMU_ICC_IDR0 \
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+ ((4 << R_ICC_IDR0_EL1_PRI_BITS_SHIFT) | \
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+ (1 << R_ICC_IDR0_EL1_ID_BITS_SHIFT))
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+
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static GICv5Common *gicv5_get_gic(CPUARMState *env)
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{
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return env->gicv5state;
@@ -220,6 +232,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.access = PL1_W, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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.writefn = gic_cdhm_write,
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},
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+ { .name = "ICC_IDR0_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 2,
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+ .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
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+ .resetvalue = QEMU_ICC_IDR0,
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+ },
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{ .name = "ICC_ICSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 4,
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.access = PL1_RW, .type = ARM_CP_NO_RAW,