hw/cxl: Physical Port Info FMAPI - update to current spec and add defines.
Add a new cxl/cxl_ports.h header for field definitions related only to port commands. Bring field naming up to date with spec as 'version' bitmasks have been replaced with bitmasks of the specific features. Fix a small issue where a reserved value for USP was set to 2 rather than 0. Signed-off-by: Arpit Kumar <arpit1.kumar@samsung.com> Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260204173223.44122-2-Jonathan.Cameron@huawei.com>
Arpit Kumar committed
Feb 4, 2026 at 17:32 UTC
7df839591cf9354f7cc054ff6d01e16d46ff9f33
2 files changed
+73
-11
hw/cxl/cxl-mailbox-utils.c
+20
-11
@@ -15,6 +15,7 @@
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#include "hw/cxl/cxl.h"
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#include "hw/cxl/cxl_events.h"
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#include "hw/cxl/cxl_mailbox.h"
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+#include "hw/cxl/cxl_port.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-bridge/cxl_upstream_port.h"
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#include "qemu/cutils.h"
@@ -565,16 +566,16 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
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} QEMU_PACKED *in;
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/*
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- * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block
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+ * CXL r3.2 Table 7-19: Get Physical Port State Port Information Block
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* Format
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*/
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struct cxl_fmapi_port_state_info_block {
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uint8_t port_id;
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uint8_t config_state;
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- uint8_t connected_device_cxl_version;
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+ uint8_t connected_device_mode;
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uint8_t rsv1;
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uint8_t connected_device_type;
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- uint8_t port_cxl_version_bitmask;
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+ uint8_t supported_cxl_mode_bitmask;
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uint8_t max_link_width;
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uint8_t negotiated_link_width;
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uint8_t supported_link_speeds_vector;
@@ -623,21 +624,30 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
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if (port_dev) { /* DSP */
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PCIDevice *ds_dev = pci_bridge_get_sec_bus(PCI_BRIDGE(port_dev))
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->devices[0];
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- port->config_state = 3;
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+ port->config_state = CXL_PORT_CONFIG_STATE_DSP;
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if (ds_dev) {
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if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) {
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- port->connected_device_type = 5; /* Assume MLD for now */
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+ /* Assume MLD for now */
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+ port->connected_device_type =
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+ CXL_PORT_CONNECTED_DEV_TYPE_3_MLD;
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} else {
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- port->connected_device_type = 1;
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+ port->connected_device_type =
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+ CXL_PORT_CONNECTED_DEV_TYPE_PCIE;
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+ port->connected_device_mode =
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+ CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN;
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+
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}
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} else {
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- port->connected_device_type = 0;
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+ port->connected_device_type = CXL_PORT_CONNECTED_DEV_TYPE_NONE;
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+ port->connected_device_mode =
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+ CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN;
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}
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port->supported_ld_count = 3;
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} else if (usp->port == in->ports[i]) { /* USP */
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port_dev = PCI_DEVICE(usp);
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- port->config_state = 4;
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- port->connected_device_type = 0;
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+ port->config_state = CXL_PORT_CONFIG_STATE_USP;
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+ port->connected_device_type = 0; /* Reserved for USP */
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+ port->connected_device_mode = 0; /* Reserved for USP */
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} else {
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return CXL_MBOX_INVALID_INPUT;
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}
@@ -667,8 +677,7 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
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port->ltssm_state = 0x7;
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port->first_lane_num = 0;
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port->link_state = 0;
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- port->port_cxl_version_bitmask = 0x2;
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- port->connected_device_cxl_version = 0x2;
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+ port->supported_cxl_mode_bitmask = CXL_PORT_SUPPORTS_68B_VH;
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}
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pl_size = sizeof(*out) + sizeof(*out->ports) * in->num_ports;
include/hw/cxl/cxl_port.h
new
+53
@@ -0,0 +1,53 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+
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+#ifndef CXL_PORT_H
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+#define CXL_PORT_H
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+
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+/* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block Format */
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+#define CXL_PORT_CONFIG_STATE_DISABLED 0x0
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+#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1
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+#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2
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+#define CXL_PORT_CONFIG_STATE_DSP 0x3
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+#define CXL_PORT_CONFIG_STATE_USP 0x4
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+#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5
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+#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF
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+
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+#define CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN 0x00
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+#define CXL_PORT_CONNECTED_DEV_MODE_RCD 0x01
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+#define CXL_PORT_CONNECTED_DEV_MODE_68B_VH 0x02
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+#define CXL_PORT_CONNECTED_DEV_MODE_256B 0x03
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+#define CXL_PORT_CONNECTED_DEV_MODE_LO_256B 0x04
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+#define CXL_PORT_CONNECTED_DEV_MODE_PBR 0x05
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+
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+#define CXL_PORT_CONNECTED_DEV_TYPE_NONE 0x00
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+#define CXL_PORT_CONNECTED_DEV_TYPE_PCIE 0x01
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+#define CXL_PORT_CONNECTED_DEV_TYPE_1 0x02
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+#define CXL_PORT_CONNECTED_DEV_TYPE_2_OR_HBR_SWITCH 0x03
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+#define CXL_PORT_CONNECTED_DEV_TYPE_3_SLD 0x04
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+#define CXL_PORT_CONNECTED_DEV_TYPE_3_MLD 0x05
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+#define CXL_PORT_CONNECTED_DEV_PBR_COMPONENT 0x06
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+
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+#define CXL_PORT_SUPPORTS_RCD BIT(0)
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+#define CXL_PORT_SUPPORTS_68B_VH BIT(1)
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+#define CXL_PORT_SUPPORTS_256B BIT(2)
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+#define CXL_PORT_SUPPORTS_LO_256B BIT(3)
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+#define CXL_PORT_SUPPORTS_PBR BIT(4)
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+
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+#define CXL_PORT_LTSSM_DETECT 0x00
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+#define CXL_PORT_LTSSM_POLLING 0x01
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+#define CXL_PORT_LTSSM_CONFIGURATION 0x02
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+#define CXL_PORT_LTSSM_RECOVERY 0x03
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+#define CXL_PORT_LTSSM_L0 0x04
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+#define CXL_PORT_LTSSM_L0S 0x05
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+#define CXL_PORT_LTSSM_L1 0x06
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+#define CXL_PORT_LTSSM_L2 0x07
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+#define CXL_PORT_LTSSM_DISABLED 0x08
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+#define CXL_PORT_LTSSM_LOOPBACK 0x09
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+#define CXL_PORT_LTSSM_HOT_RESET 0x0A
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+
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+#define CXL_PORT_LINK_STATE_FLAG_LANE_REVERSED BIT(0)
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+#define CXL_PORT_LINK_STATE_FLAG_PERST_ASSERTED BIT(1)
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+#define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2)
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+#define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3)
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+
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+#endif /* CXL_PORT_H */