target: convert TABS indentation to spaces for consistency
To follow consistent coding style, convert TABS indentation to spaces for consistency. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/372 Signed-off-by: Tanya Agarwal <tanyaagarwal25699@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20260328170913.3673-1-tanyaagarwal25699@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Tanya Agarwal committed
Mar 28, 2026 at 22:39 UTC
7dfea705cba6dfedd5a33d46f94a73d5c8bcedd9
5 files changed
+347
-347
target/alpha/cpu.h
+3
-3
@@ -311,9 +311,9 @@ enum {
311
};
312
313
/* Alpha-specific interrupt pending bits. */
314
-#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
315
-#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
316
-#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
314
+#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
315
+#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
316
+#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
317
318
/* OSF/1 Page table bits. */
319
enum {
target/i386/cpu.h
+20
-20
@@ -417,12 +417,12 @@ typedef enum X86Seg {
417
#define MSR_IA32_CORE_CAPABILITY 0xcf
418
419
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
420
-#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
420
+#define ARCH_CAP_TSX_CTRL_MSR (1 << 7)
421
422
#define MSR_IA32_PERF_CAPABILITIES 0x345
423
#define PERF_CAP_LBR_FMT 0x3f
424
425
-#define MSR_IA32_TSX_CTRL 0x122
425
+#define MSR_IA32_TSX_CTRL 0x122
426
#define MSR_IA32_TSCDEADLINE 0x6e0
427
#define MSR_IA32_PKRS 0x6e1
428
#define MSR_RAPL_POWER_UNIT 0x00000606
@@ -1482,24 +1482,24 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
1482
#define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1483
#endif
1484
1485
-#define EXCP00_DIVZ 0
1486
-#define EXCP01_DB 1
1487
-#define EXCP02_NMI 2
1488
-#define EXCP03_INT3 3
1489
-#define EXCP04_INTO 4
1490
-#define EXCP05_BOUND 5
1491
-#define EXCP06_ILLOP 6
1492
-#define EXCP07_PREX 7
1493
-#define EXCP08_DBLE 8
1494
-#define EXCP09_XERR 9
1495
-#define EXCP0A_TSS 10
1496
-#define EXCP0B_NOSEG 11
1497
-#define EXCP0C_STACK 12
1498
-#define EXCP0D_GPF 13
1499
-#define EXCP0E_PAGE 14
1500
-#define EXCP10_COPR 16
1501
-#define EXCP11_ALGN 17
1502
-#define EXCP12_MCHK 18
1485
+#define EXCP00_DIVZ 0
1486
+#define EXCP01_DB 1
1487
+#define EXCP02_NMI 2
1488
+#define EXCP03_INT3 3
1489
+#define EXCP04_INTO 4
1490
+#define EXCP05_BOUND 5
1491
+#define EXCP06_ILLOP 6
1492
+#define EXCP07_PREX 7
1493
+#define EXCP08_DBLE 8
1494
+#define EXCP09_XERR 9
1495
+#define EXCP0A_TSS 10
1496
+#define EXCP0B_NOSEG 11
1497
+#define EXCP0C_STACK 12
1498
+#define EXCP0D_GPF 13
1499
+#define EXCP0E_PAGE 14
1500
+#define EXCP10_COPR 16
1501
+#define EXCP11_ALGN 17
1502
+#define EXCP12_MCHK 18
1503
1504
#define EXCP_VMEXIT 0x100 /* only for system emulation */
1505
#define EXCP_SYSCALL 0x101 /* only for user emulation */
target/i386/svm.h
+154
-154
@@ -54,88 +54,88 @@
54
55
#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
56
57
-#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
58
-#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
59
-#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
60
-#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
57
+#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
58
+#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
59
+#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
60
+#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
61
62
#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
63
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
64
65
-#define SVM_EXIT_READ_CR0 0x000
66
-#define SVM_EXIT_READ_CR3 0x003
67
-#define SVM_EXIT_READ_CR4 0x004
68
-#define SVM_EXIT_READ_CR8 0x008
69
-#define SVM_EXIT_WRITE_CR0 0x010
70
-#define SVM_EXIT_WRITE_CR3 0x013
71
-#define SVM_EXIT_WRITE_CR4 0x014
72
-#define SVM_EXIT_WRITE_CR8 0x018
73
-#define SVM_EXIT_READ_DR0 0x020
74
-#define SVM_EXIT_READ_DR1 0x021
75
-#define SVM_EXIT_READ_DR2 0x022
76
-#define SVM_EXIT_READ_DR3 0x023
77
-#define SVM_EXIT_READ_DR4 0x024
78
-#define SVM_EXIT_READ_DR5 0x025
79
-#define SVM_EXIT_READ_DR6 0x026
80
-#define SVM_EXIT_READ_DR7 0x027
81
-#define SVM_EXIT_WRITE_DR0 0x030
82
-#define SVM_EXIT_WRITE_DR1 0x031
83
-#define SVM_EXIT_WRITE_DR2 0x032
84
-#define SVM_EXIT_WRITE_DR3 0x033
85
-#define SVM_EXIT_WRITE_DR4 0x034
86
-#define SVM_EXIT_WRITE_DR5 0x035
87
-#define SVM_EXIT_WRITE_DR6 0x036
88
-#define SVM_EXIT_WRITE_DR7 0x037
65
+#define SVM_EXIT_READ_CR0 0x000
66
+#define SVM_EXIT_READ_CR3 0x003
67
+#define SVM_EXIT_READ_CR4 0x004
68
+#define SVM_EXIT_READ_CR8 0x008
69
+#define SVM_EXIT_WRITE_CR0 0x010
70
+#define SVM_EXIT_WRITE_CR3 0x013
71
+#define SVM_EXIT_WRITE_CR4 0x014
72
+#define SVM_EXIT_WRITE_CR8 0x018
73
+#define SVM_EXIT_READ_DR0 0x020
74
+#define SVM_EXIT_READ_DR1 0x021
75
+#define SVM_EXIT_READ_DR2 0x022
76
+#define SVM_EXIT_READ_DR3 0x023
77
+#define SVM_EXIT_READ_DR4 0x024
78
+#define SVM_EXIT_READ_DR5 0x025
79
+#define SVM_EXIT_READ_DR6 0x026
80
+#define SVM_EXIT_READ_DR7 0x027
81
+#define SVM_EXIT_WRITE_DR0 0x030
82
+#define SVM_EXIT_WRITE_DR1 0x031
83
+#define SVM_EXIT_WRITE_DR2 0x032
84
+#define SVM_EXIT_WRITE_DR3 0x033
85
+#define SVM_EXIT_WRITE_DR4 0x034
86
+#define SVM_EXIT_WRITE_DR5 0x035
87
+#define SVM_EXIT_WRITE_DR6 0x036
88
+#define SVM_EXIT_WRITE_DR7 0x037
89
#define SVM_EXIT_EXCP_BASE 0x040
90
-#define SVM_EXIT_INTR 0x060
91
-#define SVM_EXIT_NMI 0x061
92
-#define SVM_EXIT_SMI 0x062
93
-#define SVM_EXIT_INIT 0x063
94
-#define SVM_EXIT_VINTR 0x064
95
-#define SVM_EXIT_CR0_SEL_WRITE 0x065
96
-#define SVM_EXIT_IDTR_READ 0x066
97
-#define SVM_EXIT_GDTR_READ 0x067
98
-#define SVM_EXIT_LDTR_READ 0x068
99
-#define SVM_EXIT_TR_READ 0x069
100
-#define SVM_EXIT_IDTR_WRITE 0x06a
101
-#define SVM_EXIT_GDTR_WRITE 0x06b
102
-#define SVM_EXIT_LDTR_WRITE 0x06c
103
-#define SVM_EXIT_TR_WRITE 0x06d
104
-#define SVM_EXIT_RDTSC 0x06e
105
-#define SVM_EXIT_RDPMC 0x06f
106
-#define SVM_EXIT_PUSHF 0x070
107
-#define SVM_EXIT_POPF 0x071
108
-#define SVM_EXIT_CPUID 0x072
109
-#define SVM_EXIT_RSM 0x073
110
-#define SVM_EXIT_IRET 0x074
111
-#define SVM_EXIT_SWINT 0x075
112
-#define SVM_EXIT_INVD 0x076
113
-#define SVM_EXIT_PAUSE 0x077
114
-#define SVM_EXIT_HLT 0x078
115
-#define SVM_EXIT_INVLPG 0x079
116
-#define SVM_EXIT_INVLPGA 0x07a
117
-#define SVM_EXIT_IOIO 0x07b
118
-#define SVM_EXIT_MSR 0x07c
119
-#define SVM_EXIT_TASK_SWITCH 0x07d
120
-#define SVM_EXIT_FERR_FREEZE 0x07e
121
-#define SVM_EXIT_SHUTDOWN 0x07f
122
-#define SVM_EXIT_VMRUN 0x080
123
-#define SVM_EXIT_VMMCALL 0x081
124
-#define SVM_EXIT_VMLOAD 0x082
125
-#define SVM_EXIT_VMSAVE 0x083
126
-#define SVM_EXIT_STGI 0x084
127
-#define SVM_EXIT_CLGI 0x085
128
-#define SVM_EXIT_SKINIT 0x086
129
-#define SVM_EXIT_RDTSCP 0x087
130
-#define SVM_EXIT_ICEBP 0x088
131
-#define SVM_EXIT_WBINVD 0x089
90
+#define SVM_EXIT_INTR 0x060
91
+#define SVM_EXIT_NMI 0x061
92
+#define SVM_EXIT_SMI 0x062
93
+#define SVM_EXIT_INIT 0x063
94
+#define SVM_EXIT_VINTR 0x064
95
+#define SVM_EXIT_CR0_SEL_WRITE 0x065
96
+#define SVM_EXIT_IDTR_READ 0x066
97
+#define SVM_EXIT_GDTR_READ 0x067
98
+#define SVM_EXIT_LDTR_READ 0x068
99
+#define SVM_EXIT_TR_READ 0x069
100
+#define SVM_EXIT_IDTR_WRITE 0x06a
101
+#define SVM_EXIT_GDTR_WRITE 0x06b
102
+#define SVM_EXIT_LDTR_WRITE 0x06c
103
+#define SVM_EXIT_TR_WRITE 0x06d
104
+#define SVM_EXIT_RDTSC 0x06e
105
+#define SVM_EXIT_RDPMC 0x06f
106
+#define SVM_EXIT_PUSHF 0x070
107
+#define SVM_EXIT_POPF 0x071
108
+#define SVM_EXIT_CPUID 0x072
109
+#define SVM_EXIT_RSM 0x073
110
+#define SVM_EXIT_IRET 0x074
111
+#define SVM_EXIT_SWINT 0x075
112
+#define SVM_EXIT_INVD 0x076
113
+#define SVM_EXIT_PAUSE 0x077
114
+#define SVM_EXIT_HLT 0x078
115
+#define SVM_EXIT_INVLPG 0x079
116
+#define SVM_EXIT_INVLPGA 0x07a
117
+#define SVM_EXIT_IOIO 0x07b
118
+#define SVM_EXIT_MSR 0x07c
119
+#define SVM_EXIT_TASK_SWITCH 0x07d
120
+#define SVM_EXIT_FERR_FREEZE 0x07e
121
+#define SVM_EXIT_SHUTDOWN 0x07f
122
+#define SVM_EXIT_VMRUN 0x080
123
+#define SVM_EXIT_VMMCALL 0x081
124
+#define SVM_EXIT_VMLOAD 0x082
125
+#define SVM_EXIT_VMSAVE 0x083
126
+#define SVM_EXIT_STGI 0x084
127
+#define SVM_EXIT_CLGI 0x085
128
+#define SVM_EXIT_SKINIT 0x086
129
+#define SVM_EXIT_RDTSCP 0x087
130
+#define SVM_EXIT_ICEBP 0x088
131
+#define SVM_EXIT_WBINVD 0x089
132
/* only included in documentation, maybe wrong */
133
-#define SVM_EXIT_MONITOR 0x08a
134
-#define SVM_EXIT_MWAIT 0x08b
135
-#define SVM_EXIT_XSETBV 0x08d
136
-#define SVM_EXIT_NPF 0x400
133
+#define SVM_EXIT_MONITOR 0x08a
134
+#define SVM_EXIT_MWAIT 0x08b
135
+#define SVM_EXIT_XSETBV 0x08d
136
+#define SVM_EXIT_NPF 0x400
137
138
-#define SVM_EXIT_ERR -1
138
+#define SVM_EXIT_ERR -1
139
140
#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
141
@@ -146,96 +146,96 @@
146
147
#define SVM_CR0_RESERVED_MASK 0xffffffff00000000U
148
149
-#define SVM_MSRPM_SIZE (1ULL << 13)
150
-#define SVM_IOPM_SIZE ((1ULL << 13) + 1)
149
+#define SVM_MSRPM_SIZE (1ULL << 13)
150
+#define SVM_IOPM_SIZE ((1ULL << 13) + 1)
151
152
struct QEMU_PACKED vmcb_control_area {
153
- uint16_t intercept_cr_read;
154
- uint16_t intercept_cr_write;
155
- uint16_t intercept_dr_read;
156
- uint16_t intercept_dr_write;
157
- uint32_t intercept_exceptions;
158
- uint64_t intercept;
159
- uint8_t reserved_1[44];
160
- uint64_t iopm_base_pa;
161
- uint64_t msrpm_base_pa;
162
- uint64_t tsc_offset;
163
- uint32_t asid;
164
- uint8_t tlb_ctl;
165
- uint8_t reserved_2[3];
166
- uint32_t int_ctl;
167
- uint32_t int_vector;
168
- uint32_t int_state;
169
- uint8_t reserved_3[4];
170
- uint64_t exit_code;
171
- uint64_t exit_info_1;
172
- uint64_t exit_info_2;
173
- uint32_t exit_int_info;
174
- uint32_t exit_int_info_err;
175
- uint64_t nested_ctl;
176
- uint8_t reserved_4[16];
177
- uint32_t event_inj;
178
- uint32_t event_inj_err;
179
- uint64_t nested_cr3;
180
- uint64_t lbr_ctl;
181
- uint8_t reserved_5[832];
153
+ uint16_t intercept_cr_read;
154
+ uint16_t intercept_cr_write;
155
+ uint16_t intercept_dr_read;
156
+ uint16_t intercept_dr_write;
157
+ uint32_t intercept_exceptions;
158
+ uint64_t intercept;
159
+ uint8_t reserved_1[44];
160
+ uint64_t iopm_base_pa;
161
+ uint64_t msrpm_base_pa;
162
+ uint64_t tsc_offset;
163
+ uint32_t asid;
164
+ uint8_t tlb_ctl;
165
+ uint8_t reserved_2[3];
166
+ uint32_t int_ctl;
167
+ uint32_t int_vector;
168
+ uint32_t int_state;
169
+ uint8_t reserved_3[4];
170
+ uint64_t exit_code;
171
+ uint64_t exit_info_1;
172
+ uint64_t exit_info_2;
173
+ uint32_t exit_int_info;
174
+ uint32_t exit_int_info_err;
175
+ uint64_t nested_ctl;
176
+ uint8_t reserved_4[16];
177
+ uint32_t event_inj;
178
+ uint32_t event_inj_err;
179
+ uint64_t nested_cr3;
180
+ uint64_t lbr_ctl;
181
+ uint8_t reserved_5[832];
182
};
183
184
struct QEMU_PACKED vmcb_seg {
185
- uint16_t selector;
186
- uint16_t attrib;
187
- uint32_t limit;
188
- uint64_t base;
185
+ uint16_t selector;
186
+ uint16_t attrib;
187
+ uint32_t limit;
188
+ uint64_t base;
189
};
190
191
struct QEMU_PACKED vmcb_save_area {
192
- struct vmcb_seg es;
193
- struct vmcb_seg cs;
194
- struct vmcb_seg ss;
195
- struct vmcb_seg ds;
196
- struct vmcb_seg fs;
197
- struct vmcb_seg gs;
198
- struct vmcb_seg gdtr;
199
- struct vmcb_seg ldtr;
200
- struct vmcb_seg idtr;
201
- struct vmcb_seg tr;
202
- uint8_t reserved_1[43];
203
- uint8_t cpl;
204
- uint8_t reserved_2[4];
205
- uint64_t efer;
206
- uint8_t reserved_3[112];
207
- uint64_t cr4;
208
- uint64_t cr3;
209
- uint64_t cr0;
210
- uint64_t dr7;
211
- uint64_t dr6;
212
- uint64_t rflags;
213
- uint64_t rip;
214
- uint8_t reserved_4[88];
215
- uint64_t rsp;
216
- uint8_t reserved_5[24];
217
- uint64_t rax;
218
- uint64_t star;
219
- uint64_t lstar;
220
- uint64_t cstar;
221
- uint64_t sfmask;
222
- uint64_t kernel_gs_base;
223
- uint64_t sysenter_cs;
224
- uint64_t sysenter_esp;
225
- uint64_t sysenter_eip;
226
- uint64_t cr2;
227
- uint8_t reserved_6[32];
228
- uint64_t g_pat;
229
- uint64_t dbgctl;
230
- uint64_t br_from;
231
- uint64_t br_to;
232
- uint64_t last_excp_from;
233
- uint64_t last_excp_to;
192
+ struct vmcb_seg es;
193
+ struct vmcb_seg cs;
194
+ struct vmcb_seg ss;
195
+ struct vmcb_seg ds;
196
+ struct vmcb_seg fs;
197
+ struct vmcb_seg gs;
198
+ struct vmcb_seg gdtr;
199
+ struct vmcb_seg ldtr;
200
+ struct vmcb_seg idtr;
201
+ struct vmcb_seg tr;
202
+ uint8_t reserved_1[43];
203
+ uint8_t cpl;
204
+ uint8_t reserved_2[4];
205
+ uint64_t efer;
206
+ uint8_t reserved_3[112];
207
+ uint64_t cr4;
208
+ uint64_t cr3;
209
+ uint64_t cr0;
210
+ uint64_t dr7;
211
+ uint64_t dr6;
212
+ uint64_t rflags;
213
+ uint64_t rip;
214
+ uint8_t reserved_4[88];
215
+ uint64_t rsp;
216
+ uint8_t reserved_5[24];
217
+ uint64_t rax;
218
+ uint64_t star;
219
+ uint64_t lstar;
220
+ uint64_t cstar;
221
+ uint64_t sfmask;
222
+ uint64_t kernel_gs_base;
223
+ uint64_t sysenter_cs;
224
+ uint64_t sysenter_esp;
225
+ uint64_t sysenter_eip;
226
+ uint64_t cr2;
227
+ uint8_t reserved_6[32];
228
+ uint64_t g_pat;
229
+ uint64_t dbgctl;
230
+ uint64_t br_from;
231
+ uint64_t br_to;
232
+ uint64_t last_excp_from;
233
+ uint64_t last_excp_to;
234
};
235
236
struct QEMU_PACKED vmcb {
237
- struct vmcb_control_area control;
238
- struct vmcb_save_area save;
237
+ struct vmcb_control_area control;
238
+ struct vmcb_save_area save;
239
};
240
241
#endif
target/microblaze/cpu.h
+6
-6
@@ -122,9 +122,9 @@ typedef struct CPUArchState CPUMBState;
122
#define PVR0_USE_ICACHE_MASK 0x02000000
123
#define PVR0_USE_DCACHE_MASK 0x01000000
124
#define PVR0_USE_MMU_MASK 0x00800000
125
-#define PVR0_USE_BTC 0x00400000
125
+#define PVR0_USE_BTC 0x00400000
126
#define PVR0_ENDI_MASK 0x00200000
127
-#define PVR0_FAULT 0x00100000
127
+#define PVR0_FAULT 0x00100000
128
#define PVR0_VERSION_MASK 0x0000FF00
129
#define PVR0_USER1_MASK 0x000000FF
130
#define PVR0_SPROT_MASK 0x00000001
@@ -271,10 +271,10 @@ struct CPUArchState {
271
/* MSR_UM (1 << 11) */
272
/* MSR_VM (1 << 13) */
273
/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */
274
-#define D_FLAG (1 << 12) /* Bit in ESR. */
275
-#define DRTI_FLAG (1 << 16)
276
-#define DRTE_FLAG (1 << 17)
277
-#define DRTB_FLAG (1 << 18)
274
+#define D_FLAG (1 << 12) /* Bit in ESR. */
275
+#define DRTI_FLAG (1 << 16)
276
+#define DRTE_FLAG (1 << 17)
277
+#define DRTB_FLAG (1 << 18)
278
279
/* TB dependent CPUMBState. */
280
#define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \
target/sparc/asi.h
+164
-164
@@ -102,7 +102,7 @@
102
103
#define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
104
105
-#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
105
+#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
106
/* only available on SuperSparc I */
107
/* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */
108
@@ -123,20 +123,20 @@
123
#define ASI_LEON_FLUSH_PAGE 0x10
124
125
/* V9 Architecture mandary ASIs. */
126
-#define ASI_N 0x04 /* Nucleus */
127
-#define ASI_NL 0x0c /* Nucleus, little endian */
128
-#define ASI_AIUP 0x10 /* Primary, user */
129
-#define ASI_AIUS 0x11 /* Secondary, user */
130
-#define ASI_AIUPL 0x18 /* Primary, user, little endian */
131
-#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
132
-#define ASI_P 0x80 /* Primary, implicit */
133
-#define ASI_S 0x81 /* Secondary, implicit */
134
-#define ASI_PNF 0x82 /* Primary, no fault */
135
-#define ASI_SNF 0x83 /* Secondary, no fault */
136
-#define ASI_PL 0x88 /* Primary, implicit, l-endian */
137
-#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
138
-#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
139
-#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
126
+#define ASI_N 0x04 /* Nucleus */
127
+#define ASI_NL 0x0c /* Nucleus, little endian */
128
+#define ASI_AIUP 0x10 /* Primary, user */
129
+#define ASI_AIUS 0x11 /* Secondary, user */
130
+#define ASI_AIUPL 0x18 /* Primary, user, little endian */
131
+#define ASI_AIUSL 0x19 /* Secondary, user, little endian */
132
+#define ASI_P 0x80 /* Primary, implicit */
133
+#define ASI_S 0x81 /* Secondary, implicit */
134
+#define ASI_PNF 0x82 /* Primary, no fault */
135
+#define ASI_SNF 0x83 /* Secondary, no fault */
136
+#define ASI_PL 0x88 /* Primary, implicit, l-endian */
137
+#define ASI_SL 0x89 /* Secondary, implicit, l-endian */
138
+#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
139
+#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
140
141
/* SpitFire and later extended ASIs. The "(III)" marker designates
142
* UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
@@ -147,170 +147,170 @@
147
#define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */
148
#define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */
149
#define ASI_REAL 0x14 /* Real address, cacheable */
150
-#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */
150
+#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */
151
#define ASI_REAL_IO 0x15 /* Real address, non-cacheable */
152
-#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
153
-#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
154
-#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
152
+#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
153
+#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
154
+#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
155
#define ASI_REAL_L 0x1c /* Real address, cacheable, LE */
156
-#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/
156
+#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/
157
#define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */
158
-#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
159
-#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
160
-#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
161
-#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
162
-#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
158
+#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
159
+#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
160
+#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
161
+#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
162
+#define ASI_MMU 0x21 /* (4V) MMU Context Registers */
163
#define ASI_TWINX_AIUP 0x22 /* twin load, primary user */
164
#define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */
165
#define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
166
- * secondary, user
167
- */
168
-#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */
169
-#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
170
-#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */
171
-#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
166
+ * secondary, user
167
+ */
168
+#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */
169
+#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
170
+#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */
171
+#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
172
#define ASI_TWINX_N 0x27 /* twin load, nucleus */
173
#define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */
174
#define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */
175
-#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
176
-#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */
177
-#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
175
+#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
176
+#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */
177
+#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
178
#define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */
179
-#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
180
-#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
181
-#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
182
-#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
183
-#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
184
-#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
185
-#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
186
-#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
187
-#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
188
-#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
189
-#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
190
-#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
191
-#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
192
-#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
193
-#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
194
-#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
195
-#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
196
-#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
197
-#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
198
-#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
199
-#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
200
-#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
201
-#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
202
-#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
203
-#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
204
-#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
205
-#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
206
-#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
207
-#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
208
-#define ASI_UPA_CONFIG 0x4a /* UPA config space */
209
-#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
210
-#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
211
-#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
212
-#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
213
-#define ASI_AFSR 0x4c /* Async fault status register */
214
-#define ASI_AFAR 0x4d /* Async fault address register */
215
-#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
216
-#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */
217
-#define ASI_IMMU 0x50 /* Insn-MMU main register space */
218
-#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
219
-#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
220
-#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
221
-#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
222
-#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
223
-#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
224
-#define ASI_DMMU 0x58 /* Data-MMU main register space */
225
-#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
226
-#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
227
-#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
228
-#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
229
-#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
230
-#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
231
-#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
232
-#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
233
-#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
234
-#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
235
-#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
236
-#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
237
-#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
238
-#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
239
-#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
240
-#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
241
-#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
242
-#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
243
-#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
244
-#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
245
-#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
246
-#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
247
-#define ASI_EC_W 0x76 /* E-cache diag write access */
248
-#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
249
-#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
250
-#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
251
-#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
252
-#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
253
-#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
254
-#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255
-#define ASI_EC_R 0x7e /* E-cache diag read access */
256
-#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
257
-#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
258
-#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
259
-#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
260
-#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
261
-#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
179
+#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
180
+#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
181
+#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
182
+#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
183
+#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
184
+#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
185
+#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
186
+#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
187
+#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
188
+#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
189
+#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
190
+#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
191
+#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
192
+#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
193
+#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
194
+#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
195
+#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
196
+#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
197
+#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
198
+#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
199
+#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
200
+#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
201
+#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
202
+#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
203
+#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
204
+#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
205
+#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
206
+#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
207
+#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
208
+#define ASI_UPA_CONFIG 0x4a /* UPA config space */
209
+#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
210
+#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
211
+#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
212
+#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
213
+#define ASI_AFSR 0x4c /* Async fault status register */
214
+#define ASI_AFAR 0x4d /* Async fault address register */
215
+#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
216
+#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */
217
+#define ASI_IMMU 0x50 /* Insn-MMU main register space */
218
+#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
219
+#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
220
+#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
221
+#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
222
+#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
223
+#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
224
+#define ASI_DMMU 0x58 /* Data-MMU main register space */
225
+#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
226
+#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
227
+#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
228
+#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
229
+#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
230
+#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
231
+#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
232
+#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
233
+#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
234
+#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
235
+#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
236
+#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */
237
+#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
238
+#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
239
+#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
240
+#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
241
+#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
242
+#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
243
+#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
244
+#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
245
+#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
246
+#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
247
+#define ASI_EC_W 0x76 /* E-cache diag write access */
248
+#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
249
+#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
250
+#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
251
+#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
252
+#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
253
+#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
254
+#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255
+#define ASI_EC_R 0x7e /* E-cache diag read access */
256
+#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
257
+#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
258
+#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
259
+#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
260
+#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
261
+#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
262
#define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */
263
#define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */
264
-#define ASI_PIC 0xb0 /* (NG4) PIC registers */
265
-#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
266
-#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
267
-#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
268
-#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
269
-#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
270
-#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
271
-#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
272
-#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
273
-#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
274
-#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
275
-#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
276
-#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
277
-#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
278
-#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
279
-#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
280
-#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
281
-#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
282
-#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
283
-#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
284
-#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
285
-#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
286
-#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
264
+#define ASI_PIC 0xb0 /* (NG4) PIC registers */
265
+#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
266
+#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
267
+#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
268
+#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
269
+#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
270
+#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
271
+#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
272
+#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
273
+#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
274
+#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
275
+#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
276
+#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
277
+#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
278
+#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
279
+#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
280
+#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
281
+#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
282
+#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
283
+#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
284
+#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
285
+#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
286
+#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
287
#define ASI_TWINX_P 0xe2 /* twin load, primary implicit */
288
-#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
289
- * primary, implicit */
288
+#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
289
+ * primary, implicit */
290
#define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */
291
-#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
292
- * secondary, implicit */
291
+#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
292
+ * secondary, implicit */
293
#define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */
294
#define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */
295
-#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
296
-#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
297
-#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
298
- * Most-Recently-Used, primary,
299
- * implicit
300
- */
301
-#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
302
- * Most-Recently-Used, secondary,
303
- * implicit
304
- */
305
-#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
306
-#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
307
-#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
308
- * Most-Recently-Used, primary,
309
- * implicit, little-endian
310
- */
311
-#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,
312
- * Most-Recently-Used, secondary,
313
- * implicit, little-endian
314
- */
295
+#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
296
+#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
297
+#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
298
+ * Most-Recently-Used, primary,
299
+ * implicit
300
+ */
301
+#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
302
+ * Most-Recently-Used, secondary,
303
+ * implicit
304
+ */
305
+#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
306
+#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
307
+#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
308
+ * Most-Recently-Used, primary,
309
+ * implicit, little-endian
310
+ */
311
+#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,
312
+ * Most-Recently-Used, secondary,
313
+ * implicit, little-endian
314
+ */
315
316
#endif /* SPARC_ASI_H */