target/riscv: do not set defaults in cpu prop callback
Do not rely on riscv_cpu_* arrays to set rv32/rv64 CPU defaults - add them to the CPU definition like we do with all other CPUs (aside from 'max'). Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260512032926.1978818-13-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
May 12, 2026 at 00:29 UTC
7f69296d8e84c967642a7795f86c8da86f05d0dc
2 files changed
+40
-14
target/riscv/cpu.c
+40
@@ -3076,6 +3076,26 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
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.cfg.max_satp_mode = VM_1_10_SV32,
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.misa_mxl_max = MXL_RV32,
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+
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+ /* Default extensions as of QEMU 11.1. */
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+ .cfg.ext_zicbom = true,
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+ .cfg.ext_zicbop = true,
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+ .cfg.ext_zicboz = true,
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+ .cfg.ext_zicntr = true,
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+ .cfg.ext_zicsr = true,
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+ .cfg.ext_zifencei = true,
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+ .cfg.ext_zihintntl = true,
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+ .cfg.ext_zihintpause = true,
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+ .cfg.ext_zihpm = true,
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+ .cfg.ext_zawrs = true,
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+ .cfg.ext_zfa = true,
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+ .cfg.ext_zba = true,
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+ .cfg.ext_zbb = true,
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+ .cfg.ext_zbc = true,
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+ .cfg.ext_zbs = true,
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+ .cfg.ext_sstc = true,
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+ .cfg.ext_svadu = true,
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+ .cfg.ext_svvptc = true,
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),
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,
@@ -3128,6 +3148,26 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
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.cfg.max_satp_mode = VM_1_10_SV57,
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.misa_mxl_max = MXL_RV64,
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+
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+ /* Default extensions as of QEMU 11.1. */
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+ .cfg.ext_zicbom = true,
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+ .cfg.ext_zicbop = true,
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+ .cfg.ext_zicboz = true,
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+ .cfg.ext_zicntr = true,
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+ .cfg.ext_zicsr = true,
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+ .cfg.ext_zifencei = true,
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+ .cfg.ext_zihintntl = true,
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+ .cfg.ext_zihintpause = true,
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+ .cfg.ext_zihpm = true,
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+ .cfg.ext_zawrs = true,
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+ .cfg.ext_zfa = true,
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+ .cfg.ext_zba = true,
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+ .cfg.ext_zbb = true,
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+ .cfg.ext_zbc = true,
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+ .cfg.ext_zbs = true,
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+ .cfg.ext_sstc = true,
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+ .cfg.ext_svadu = true,
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+ .cfg.ext_svvptc = true,
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),
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,
target/riscv/tcg/tcg-cpu.c
-14
@@ -1553,24 +1553,10 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
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static void cpu_add_multi_ext_prop(Object *cpu_obj,
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const RISCVCPUMultiExtConfig *multi_cfg)
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{
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- bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
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-
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object_property_add(cpu_obj, multi_cfg->name, "bool",
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cpu_get_multi_ext_cfg,
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cpu_set_multi_ext_cfg,
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NULL, (void *)&multi_cfg->offset);
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-
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- if (!generic_cpu) {
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- return;
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- }
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-
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- /*
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- * Set def val directly instead of using
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- * object_property_set_bool() to save the set()
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- * callback hash for user inputs.
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- */
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- isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
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- multi_cfg->enabled);
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}
1561
1562
static void riscv_cpu_add_multiext_prop_array(Object *obj,