hw/intc: Skeleton of GICv5 IRS classes
This commit adds the skeleton of the classes for the GICv5 IRS (Interrupt Routing Service). Since the IRS is the main (and only non-optional) part of the GICv5 outside the CPU, we call it simply "GICv5", in line with how we've handled the GICv3. Since we're definitely going to need to have support for KVM VMs where we present the guest with a GICv5, we use the same split between an abstract "common" and a concrete specific-to-TCG child class that we have for the various GICv3 components. This avoids having to refactor out the base class later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260327111700.795099-4-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:15 UTC
836026f1ddd58d4d20f24d3cec45c5bcb1e9a791
6 files changed
+142
hw/intc/Kconfig
+5
@@ -35,6 +35,11 @@ config ARM_GIC_KVM
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bool
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depends on ARM_GIC && KVM
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+config ARM_GICV5
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+ bool
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+ depends on TCG
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+ select MSI_NONBROKEN
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+
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config XICS
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bool
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hw/intc/arm_gicv5.c
new
+39
@@ -0,0 +1,39 @@
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+/*
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+ * ARM GICv5 emulation: Interrupt Routing Service (IRS)
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+ *
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+ * Copyright (c) 2025 Linaro Limited
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/intc/arm_gicv5.h"
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+
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+OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON)
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+
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+static void gicv5_reset_hold(Object *obj, ResetType type)
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+{
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+ GICv5 *s = ARM_GICV5(obj);
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+ GICv5Class *c = ARM_GICV5_GET_CLASS(s);
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+
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+ if (c->parent_phases.hold) {
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+ c->parent_phases.hold(obj, type);
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+ }
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+}
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+
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+static void gicv5_init(Object *obj)
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+{
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+}
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+
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+static void gicv5_finalize(Object *obj)
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+{
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+}
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+
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+static void gicv5_class_init(ObjectClass *oc, const void *data)
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+{
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+ ResettableClass *rc = RESETTABLE_CLASS(oc);
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+ GICv5Class *gc = ARM_GICV5_CLASS(oc);
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+
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+ resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL,
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+ &gc->parent_phases);
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+}
hw/intc/arm_gicv5_common.c
new
+31
@@ -0,0 +1,31 @@
1
+/*
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+ * Common base class for GICv5 IRS
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+ *
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+ * Copyright (c) 2025 Linaro Limited
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "hw/intc/arm_gicv5_common.h"
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+
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+OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, SYS_BUS_DEVICE)
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+
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+static void gicv5_common_reset_hold(Object *obj, ResetType type)
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+{
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+}
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+
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+static void gicv5_common_init(Object *obj)
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+{
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+}
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+
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+static void gicv5_common_finalize(Object *obj)
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+{
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+}
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+
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+static void gicv5_common_class_init(ObjectClass *oc, const void *data)
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+{
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+ ResettableClass *rc = RESETTABLE_CLASS(oc);
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+
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+ rc->phases.hold = gicv5_common_reset_hold;
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+}
hw/intc/meson.build
+4
@@ -12,6 +12,10 @@ system_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files(
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'arm_gicv3_its.c',
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'arm_gicv3_redist.c',
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))
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+system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files(
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+ 'arm_gicv5_common.c',
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+ 'arm_gicv5.c',
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+))
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system_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
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system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
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system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_intc.c'))
include/hw/intc/arm_gicv5.h
new
+32
@@ -0,0 +1,32 @@
1
+/*
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+ * ARM GICv5 emulation: Interrupt Routing Service (IRS)
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+ *
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+ * Copyright (c) 2025 Linaro Limited
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef HW_INTC_ARM_GICV5_H
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+#define HW_INTC_ARM_GICV5_H
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+
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+#include "qom/object.h"
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+#include "hw/core/sysbus.h"
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+#include "hw/intc/arm_gicv5_common.h"
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+
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+#define TYPE_ARM_GICV5 "arm-gicv5"
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+
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+OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5)
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+
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+/*
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+ * This class is for TCG-specific state for the GICv5.
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+ */
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+struct GICv5 {
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+ GICv5Common parent_obj;
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+};
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+
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+struct GICv5Class {
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+ GICv5CommonClass parent_class;
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+ ResettablePhases parent_phases;
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+};
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+
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+#endif
include/hw/intc/arm_gicv5_common.h
new
+31
@@ -0,0 +1,31 @@
1
+/*
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+ * Common base class for GICv5 IRS
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+ *
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+ * Copyright (c) 2025 Linaro Limited
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef HW_INTC_ARM_GICV5_COMMON_H
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+#define HW_INTC_ARM_GICV5_COMMON_H
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+
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+#include "qom/object.h"
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+#include "hw/core/sysbus.h"
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+
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+#define TYPE_ARM_GICV5_COMMON "arm-gicv5-common"
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+
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+OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON)
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+
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+/*
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+ * This class is for common state that will eventually be shared
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+ * between TCG and KVM implementations of the GICv5.
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+ */
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+struct GICv5Common {
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+ SysBusDevice parent_obj;
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+};
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+
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+struct GICv5CommonClass {
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+ SysBusDeviceClass parent_class;
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+};
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+
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+#endif