target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
The non-standard extensions, in this particular function the vendor extensions, are all riscv,isa names that starts with 'x'. In theory this is a bit slower than using riscv_cpu_vendor_exts (isa_edata_arr is longer) but riscv_cpu_update_misa_x() is executed only once during finalize(), i.e. not a hot path. We're accepting a tiny performance hit as as a tradeoff for the code simplication we'll have later by removing all riscv_cpu_* arrays. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260512032926.1978818-9-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Daniel Henrique Barboza committed
May 12, 2026 at 00:29 UTC
85136e097a95d74cc86e3e78977e0c98f5697570
1 file changed
+4
-3
target/riscv/tcg/tcg-cpu.c
+4
-3
@@ -1155,10 +1155,11 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
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static void riscv_cpu_update_misa_x(RISCVCPU *cpu)
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{
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CPURISCVState *env = &cpu->env;
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- const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
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+ const RISCVIsaExtData *edata;
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- for (int i = 0; arr[i].name != NULL; i++) {
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- if (isa_ext_is_enabled(cpu, arr[i].offset)) {
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+ for (edata = isa_edata_arr; edata && edata->name; edata++) {
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+ if (edata->name[0] == 'x'
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+ && isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
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riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);
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break;
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}