@samitouri / QOSamiQemu / commits / 85136e097a

target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()

The non-standard extensions, in this particular function the vendor extensions, are all riscv,isa names that starts with 'x'. In theory this is a bit slower than using riscv_cpu_vendor_exts (isa_edata_arr is longer) but riscv_cpu_update_misa_x() is executed only once during finalize(), i.e. not a hot path. We're accepting a tiny performance hit as as a tradeoff for the code simplication we'll have later by removing all riscv_cpu_* arrays. Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260512032926.1978818-9-daniel.barboza@oss.qualcomm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Daniel Henrique Barboza committed May 12, 2026 at 00:29 UTC 85136e097a95d74cc86e3e78977e0c98f5697570
1 file changed +4 -3
target/riscv/tcg/tcg-cpu.c
+4 -3
@@ -1155,10 +1155,11 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
1155 static void riscv_cpu_update_misa_x(RISCVCPU *cpu)
1156 {
1157 CPURISCVState *env = &cpu->env;
1158 - const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
1158 + const RISCVIsaExtData *edata;
1159
1160 - for (int i = 0; arr[i].name != NULL; i++) {
1161 - if (isa_ext_is_enabled(cpu, arr[i].offset)) {
1160 + for (edata = isa_edata_arr; edata && edata->name; edata++) {
1161 + if (edata->name[0] == 'x'
1162 + && isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
1163 riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);
1164 break;
1165 }