hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi
Add a ppi_base parameter to tpm_build_ppi_acpi() instead of hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where PPI memory is dynamically allocated by the platform bus and the address is not known at compile time. Update the x86 callers (ISA TIS and CRB) to pass TPM_PPI_ADDR_BASE explicitly. No behavioral change. Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260327173209.148180-3-mbawa@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Mohammadfaiz Bawa committed
Mar 27, 2026 at 23:02 UTC
859252e13bb5a84bb9d25490168ec37e621ab92a
4 files changed
+8
-7
hw/acpi/tpm.c
+4
-4
@@ -20,7 +20,7 @@
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#include "qapi/error.h"
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#include "hw/acpi/tpm.h"
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-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
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+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
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{
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Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,
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*not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;
@@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
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*/
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aml_append(dev,
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aml_operation_region("TPP2", AML_SYSTEM_MEMORY,
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- aml_int(TPM_PPI_ADDR_BASE + 0x100),
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+ aml_int(ppi_base + 0x100),
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0x5A));
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field = aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("PPIN", 8));
@@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
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aml_append(dev,
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aml_operation_region(
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"TPP3", AML_SYSTEM_MEMORY,
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- aml_int(TPM_PPI_ADDR_BASE +
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+ aml_int(ppi_base +
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0x15a /* movv, docs/specs/tpm.rst */),
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0x1));
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field = aml_field("TPP3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
@@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
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aml_append(method,
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aml_operation_region("TPP1", AML_SYSTEM_MEMORY,
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- aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));
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+ aml_add(aml_int(ppi_base), op, NULL), 0x1));
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field = aml_field("TPP1", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("TPPF", 8));
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aml_append(method, field);
hw/i386/acpi-build.c
+1
-1
@@ -1219,7 +1219,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
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aml_append(dev, aml_name_decl("_UID", aml_int(1)));
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- tpm_build_ppi_acpi(tpm, dev);
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+ tpm_build_ppi_acpi(tpm, dev, TPM_PPI_ADDR_BASE);
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aml_append(sb_scope, dev);
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}
hw/tpm/tpm_tis_isa.c
+1
-1
@@ -159,7 +159,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
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*/
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/* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */
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aml_append(dev, aml_name_decl("_CRS", crs));
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- tpm_build_ppi_acpi(ti, dev);
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+ tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);
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aml_append(scope, dev);
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}
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include/hw/acpi/tpm.h
+2
-1
@@ -20,6 +20,7 @@
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#include "hw/core/registerfields.h"
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#include "hw/acpi/aml-build.h"
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#include "system/tpm.h"
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+#include "exec/hwaddr.h"
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#ifdef CONFIG_TPM
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@@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)
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*/
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#define TPM_I2C_INT_ENABLE_MASK 0x0
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-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
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+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);
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#endif /* CONFIG_TPM */
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