@samitouri / QOSamiQemu / commits / 85ea0ab9e7

target: Rename get_phys_page_debug to get_phys_addr_debug

Now that we have ensured that all implementations of the get_phys_page_debug method handle a non-page-aligned input and return the corresponding non-page-aligned output, the name of the method is somewhat misleading. Rename it to get_phys_addr_debug. This commit was produced with the commands sed -i -e 's/_cpu_get_phys_page_debug/_cpu_get_phys_addr_debug/g;s/\<get_phys_page_debug\>/get_phys_addr_debug/g' $(git grep -l get_phys_page_debug) sed -i -e 's/_cpu_get_phys_page_attrs_debug/_cpu_get_phys_addr_attrs_debug/g;s/\<get_phys_page_attrs_debug\>/get_phys_addr_attrs_debug/g' $(git grep -l get_phys_page_attrs_debug) which catches all references to the method name itself plus the functions which each target uses as the method implementation, but (deliberately) not the cpu_phys_get_page_debug() and cpu_phys_get_page_attrs_debug() wrapper functions or their callers. (We'll deal with those in the next commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260417173105.1648172-9-peter.maydell@linaro.org Message-ID: <20260430093810.2762539-10-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Peter Maydell committed Apr 30, 2026 at 10:37 UTC 85ea0ab9e7f2dd16517670e671ff43f2a469304e

56 files changed +62 -62

hw/core/cpu-system.c

+3 -3

@@ -60,13 +60,13 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,

60 {

61 hwaddr paddr;

63 - if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) {

64 - paddr = cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr,

63 + if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) {

64 + paddr = cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr,

65 attrs);

66 } else {

67 /* Fallback for CPUs which don't implement the _attrs_ hook */

68 *attrs = MEMTXATTRS_UNSPECIFIED;

69 - paddr = cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr);

69 + paddr = cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr);

70 }

71 /* Indicate that this is a debug access. */

72 attrs->debug = 1;

include/hw/core/sysemu-cpu-ops.h

+5 -5

@@ -30,17 +30,17 @@ typedef struct SysemuCPUOps {

30 */

31 bool (*get_paging_enabled)(const CPUState *cpu);

32 /**

33 - * @get_phys_page_debug: Callback for obtaining a physical address.

33 + * @get_phys_addr_debug: Callback for obtaining a physical address.

34 */

35 - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);

35 + hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr);

36 /**

37 - * @get_phys_page_attrs_debug: Callback for obtaining a physical address

37 + * @get_phys_addr_attrs_debug: Callback for obtaining a physical address

38 * and the associated memory transaction attributes to use for the

39 * access.

40 * CPUs which use memory transaction attributes should implement this

41 - * instead of get_phys_page_debug.

41 + * instead of get_phys_addr_debug.

42 */

43 - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,

43 + hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr,

44 MemTxAttrs *attrs);

45 /**

46 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for

target/alpha/cpu.c

+1 -1

@@ -242,7 +242,7 @@ static void alpha_cpu_initfn(Object *obj)

242

243 static const struct SysemuCPUOps alpha_sysemu_ops = {

244 .has_work = alpha_cpu_has_work,

245 - .get_phys_page_debug = alpha_cpu_get_phys_page_debug,

245 + .get_phys_addr_debug = alpha_cpu_get_phys_addr_debug,

246 };

247 #endif

248

target/alpha/cpu.h

+1 -1

@@ -282,7 +282,7 @@ extern const VMStateDescription vmstate_alpha_cpu;

282

283 void alpha_cpu_do_interrupt(CPUState *cpu);

284 bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);

285 -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

285 +hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

286 #endif /* !CONFIG_USER_ONLY */

287 void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);

288 int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);

target/alpha/helper.c

+1 -1

@@ -295,7 +295,7 @@ static int get_physical_address(CPUAlphaState *env, vaddr addr,

295 return ret;

296 }

297

298 -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

298 +hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

299 {

300 hwaddr phys;

301 int prot, fail;

target/arm/cpu.c

+1 -1

@@ -2498,7 +2498,7 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)

2498

2499 static const struct SysemuCPUOps arm_sysemu_ops = {

2500 .has_work = arm_cpu_has_work,

2501 - .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,

2501 + .get_phys_addr_attrs_debug = arm_cpu_get_phys_addr_attrs_debug,

2502 .asidx_from_attrs = arm_asidx_from_attrs,

2503 .write_elf32_note = arm_cpu_write_elf32_note,

2504 .write_elf64_note = arm_cpu_write_elf64_note,

target/arm/cpu.h

+1 -1

@@ -1260,7 +1260,7 @@ extern const VMStateDescription vmstate_arm_cpu;

1260 void arm_cpu_do_interrupt(CPUState *cpu);

1261 void arm_v7m_cpu_do_interrupt(CPUState *cpu);

1262

1263 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,

1263 +hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,

1264 MemTxAttrs *attrs);

1265

1266 typedef struct ARMGranuleProtectionConfig {

target/arm/ptw.c

+1 -1

@@ -3963,7 +3963,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr,

3963 return res.f.phys_addr;

3964 }

3965

3966 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,

3966 +hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,

3967 MemTxAttrs *attrs)

3968 {

3969 ARMCPU *cpu = ARM_CPU(cs);

target/avr/cpu.c

+1 -1

@@ -233,7 +233,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)

233

234 static const struct SysemuCPUOps avr_sysemu_ops = {

235 .has_work = avr_cpu_has_work,

236 - .get_phys_page_debug = avr_cpu_get_phys_page_debug,

236 + .get_phys_addr_debug = avr_cpu_get_phys_addr_debug,

237 };

238

239 static const TCGCPUOps avr_tcg_ops = {

target/avr/cpu.h

+1 -1

@@ -177,7 +177,7 @@ extern const struct VMStateDescription vms_avr_cpu;

177

178 void avr_cpu_do_interrupt(CPUState *cpu);

179 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);

180 -hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

180 +hwaddr avr_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

181 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);

182 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

183 int avr_print_insn(bfd_vma addr, disassemble_info *info);

target/avr/helper.c

+1 -1

@@ -107,7 +107,7 @@ void avr_cpu_do_interrupt(CPUState *cs)

107 qemu_plugin_vcpu_interrupt_cb(cs, ret);

108 }

109

110 -hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

110 +hwaddr avr_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

111 {

112 return addr; /* I assume 1:1 address correspondence */

113 }

target/hppa/cpu.c

+1 -1

@@ -244,7 +244,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)

244

245 static const struct SysemuCPUOps hppa_sysemu_ops = {

246 .has_work = hppa_cpu_has_work,

247 - .get_phys_page_debug = hppa_cpu_get_phys_page_debug,

247 + .get_phys_addr_debug = hppa_cpu_get_phys_addr_debug,

248 };

249 #endif

250

target/hppa/cpu.h

+1 -1

@@ -389,7 +389,7 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

389 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);

390 #ifndef CONFIG_USER_ONLY

391 void hppa_ptlbe(CPUHPPAState *env);

392 -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);

392 +hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr);

393 void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);

394 bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,

395 MMUAccessType access_type, int mmu_idx,

target/hppa/mem_helper.c

+1 -1

@@ -345,7 +345,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,

345 return ret;

346 }

347

348 -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

348 +hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

349 {

350 HPPACPU *cpu = HPPA_CPU(cs);

351 hwaddr phys;

target/i386/cpu.c

+1 -1

@@ -10877,7 +10877,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = {

10877 .has_work = x86_cpu_has_work,

10878 .get_memory_mapping = x86_cpu_get_memory_mapping,

10879 .get_paging_enabled = x86_cpu_get_paging_enabled,

10880 - .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,

10880 + .get_phys_addr_attrs_debug = x86_cpu_get_phys_addr_attrs_debug,

10881 .asidx_from_attrs = x86_asidx_from_attrs,

10882 .get_crash_info = x86_cpu_get_crash_info,

10883 .write_elf32_note = x86_cpu_write_elf32_note,

target/i386/cpu.h

+1 -1

@@ -2581,7 +2581,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);

2581 #ifndef CONFIG_USER_ONLY

2582 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);

2583

2584 -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,

2584 +hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,

2585 MemTxAttrs *attrs);

2586 int cpu_get_pic_interrupt(CPUX86State *s);

2587

target/i386/helper.c

+1 -1

@@ -252,7 +252,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)

252 }

253

254 #if !defined(CONFIG_USER_ONLY)

255 -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,

255 +hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,

256 MemTxAttrs *attrs)

257 {

258 X86CPU *cpu = X86_CPU(cs);

target/i386/whpx/whpx-all.c

+1 -1

@@ -247,7 +247,7 @@ struct whpx_register_set {

247 * e. Let the affected CPU run in the exclusive mode.

248 * f. Restore the original handler and the exception exit bitmap.

249 * Note that handling all corner cases related to IDT/GDT is harder

250 - * than it may seem. See x86_cpu_get_phys_page_attrs_debug() for a

250 + * than it may seem. See x86_cpu_get_phys_addr_attrs_debug() for a

251 * rough idea.

252 *

253 * 3. In order to properly support guest-level debugging in parallel with

target/loongarch/cpu-mmu.h

+1 -1

@@ -97,7 +97,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,

97 int access_type, int mmu_idx, int debug);

98 void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,

99 uint64_t *dir_width, unsigned int level);

100 -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

100 +hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

101 uint64_t loongarch_palen_mask(CPULoongArchState *env);

102

103 #endif /* LOONGARCH_CPU_MMU_H */

target/loongarch/cpu.c

+1 -1

@@ -836,7 +836,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)

836 static const struct SysemuCPUOps loongarch_sysemu_ops = {

837 .has_work = loongarch_cpu_has_work,

838 .write_elf64_note = loongarch_cpu_write_elf64_note,

839 - .get_phys_page_debug = loongarch_cpu_get_phys_page_debug,

839 + .get_phys_addr_debug = loongarch_cpu_get_phys_addr_debug,

840 };

841

842 static int64_t loongarch_cpu_get_arch_id(CPUState *cs)

target/loongarch/cpu_helper.c

+1 -1

@@ -359,7 +359,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,

359 return loongarch_map_address(env, context, access_type, mmu_idx, is_debug);

360 }

361

362 -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

362 +hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

363 {

364 CPULoongArchState *env = cpu_env(cs);

365 MMUContext context;

target/m68k/cpu.c

+1 -1

@@ -623,7 +623,7 @@ static const MonitorDef m68k_monitor_defs[] = {

623

624 static const struct SysemuCPUOps m68k_sysemu_ops = {

625 .has_work = m68k_cpu_has_work,

626 - .get_phys_page_debug = m68k_cpu_get_phys_page_debug,

626 + .get_phys_addr_debug = m68k_cpu_get_phys_addr_debug,

627 .monitor_defs = m68k_monitor_defs,

628 };

629 #endif /* !CONFIG_USER_ONLY */

target/m68k/cpu.h

+1 -1

@@ -185,7 +185,7 @@ struct M68kCPUClass {

185 #ifndef CONFIG_USER_ONLY

186 void m68k_cpu_do_interrupt(CPUState *cpu);

187 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);

188 -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

188 +hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

189 #endif /* !CONFIG_USER_ONLY */

190 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

191 int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);

target/m68k/helper.c

+1 -1

@@ -907,7 +907,7 @@ txfail:

907 return -1;

908 }

909

910 -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

910 +hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

911 {

912 CPUM68KState *env = cpu_env(cs);

913 hwaddr phys_addr;

target/microblaze/cpu.c

+1 -1

@@ -428,7 +428,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)

428

429 static const struct SysemuCPUOps mb_sysemu_ops = {

430 .has_work = mb_cpu_has_work,

431 - .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,

431 + .get_phys_addr_attrs_debug = mb_cpu_get_phys_addr_attrs_debug,

432 };

433 #endif

434

target/microblaze/cpu.h

+1 -1

@@ -369,7 +369,7 @@ struct MicroBlazeCPUClass {

369 #ifndef CONFIG_USER_ONLY

370 void mb_cpu_do_interrupt(CPUState *cs);

371 bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);

372 -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,

372 +hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,

373 MemTxAttrs *attrs);

374 #endif /* !CONFIG_USER_ONLY */

375 G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,

target/microblaze/helper.c

+1 -1

@@ -280,7 +280,7 @@ void mb_cpu_do_interrupt(CPUState *cs)

280 }

281 }

282

283 -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,

283 +hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr,

284 MemTxAttrs *attrs)

285 {

286 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);

target/mips/cpu.c

+1 -1

@@ -545,7 +545,7 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)

545

546 static const struct SysemuCPUOps mips_sysemu_ops = {

547 .has_work = mips_cpu_has_work,

548 - .get_phys_page_debug = mips_cpu_get_phys_page_debug,

548 + .get_phys_addr_debug = mips_cpu_get_phys_addr_debug,

549 .legacy_vmsd = &vmstate_mips_cpu,

550 };

551 #endif

target/mips/internal.h

+1 -1

@@ -115,7 +115,7 @@ enum {

115 int get_physical_address(CPUMIPSState *env, hwaddr *physical,

116 int *prot, target_ulong real_address,

117 MMUAccessType access_type, int mmu_idx);

118 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

118 +hwaddr mips_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

119

120 typedef struct r4k_tlb_t r4k_tlb_t;

121 struct r4k_tlb_t {

target/mips/system/physaddr.c

+1 -1

@@ -228,7 +228,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical,

228 return ret;

229 }

230

231 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

231 +hwaddr mips_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

232 {

233 CPUMIPSState *env = cpu_env(cs);

234 hwaddr phys_addr;

target/or1k/cpu.c

+1 -1

@@ -247,7 +247,7 @@ static void openrisc_any_initfn(Object *obj)

247

248 static const struct SysemuCPUOps openrisc_sysemu_ops = {

249 .has_work = openrisc_cpu_has_work,

250 - .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,

250 + .get_phys_addr_debug = openrisc_cpu_get_phys_addr_debug,

251 };

252 #endif

253

target/or1k/cpu.h

+1 -1

@@ -296,7 +296,7 @@ void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,

296 int print_insn_or1k(bfd_vma addr, disassemble_info *info);

297

298 #ifndef CONFIG_USER_ONLY

299 -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

299 +hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

300

301 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

302 MMUAccessType access_type, int mmu_idx,

target/or1k/mmu.c

+1 -1

@@ -138,7 +138,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,

138 cpu_loop_exit_restore(cs, retaddr);

139 }

140

141 -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

141 +hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

142 {

143 OpenRISCCPU *cpu = OPENRISC_CPU(cs);

144 int prot, excp, sr = cpu->env.sr;

target/ppc/cpu.h

+1 -1

@@ -1639,7 +1639,7 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

1639 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);

1640 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

1641 #ifndef CONFIG_USER_ONLY

1642 -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

1642 +hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

1643 #endif

1644 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,

1645 int cpuid, DumpState *s);

target/ppc/cpu_init.c

+1 -1

@@ -7477,7 +7477,7 @@ static void ppc_disas_set_info(const CPUState *cs, disassemble_info *info)

7477

7478 static const struct SysemuCPUOps ppc_sysemu_ops = {

7479 .has_work = ppc_cpu_has_work,

7480 - .get_phys_page_debug = ppc_cpu_get_phys_page_debug,

7480 + .get_phys_addr_debug = ppc_cpu_get_phys_addr_debug,

7481 .write_elf32_note = ppc32_cpu_write_elf32_note,

7482 .write_elf64_note = ppc64_cpu_write_elf64_note,

7483 .internal_is_big_endian = ppc_cpu_is_big_endian,

target/ppc/mmu-hash32.c

+1 -1

@@ -131,7 +131,7 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,

131 }

132

133 /*

134 - * From ppc_cpu_get_phys_page_debug, env->access_type is not set.

134 + * From ppc_cpu_get_phys_addr_debug, env->access_type is not set.

135 * Assume ACCESS_INT for that case.

136 */

137 switch (guest_visible ? env->access_type : ACCESS_INT) {

target/ppc/mmu_common.c

+1 -1

@@ -848,7 +848,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,

848 }

849 }

850

851 -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

851 +hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

852 {

853 PowerPCCPU *cpu = POWERPC_CPU(cs);

854 hwaddr raddr;

target/riscv/cpu.c

+1 -1

@@ -2730,7 +2730,7 @@ static int64_t riscv_get_arch_id(CPUState *cs)

2730

2731 static const struct SysemuCPUOps riscv_sysemu_ops = {

2732 .has_work = riscv_cpu_has_work,

2733 - .get_phys_page_debug = riscv_cpu_get_phys_page_debug,

2733 + .get_phys_addr_debug = riscv_cpu_get_phys_addr_debug,

2734 .write_elf64_note = riscv_cpu_write_elf64_note,

2735 .write_elf32_note = riscv_cpu_write_elf32_note,

2736 .monitor_get_register = riscv_monitor_get_register_legacy,

target/riscv/cpu.h

+1 -1

@@ -629,7 +629,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,

629 MMUAccessType access_type,

630 int mmu_idx, MemTxAttrs attrs,

631 MemTxResult response, uintptr_t retaddr);

632 -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

632 +hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

633 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);

634 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);

635 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);

target/riscv/cpu_helper.c

+1 -1

@@ -1710,7 +1710,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,

1710 env->two_stage_indirect_lookup = two_stage_indirect;

1711 }

1712

1713 -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

1713 +hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

1714 {

1715 RISCVCPU *cpu = RISCV_CPU(cs);

1716 CPURISCVState *env = &cpu->env;

target/rx/cpu.c

+1 -1

@@ -209,7 +209,7 @@ static void rx_cpu_init(Object *obj)

209

210 static const struct SysemuCPUOps rx_sysemu_ops = {

211 .has_work = rx_cpu_has_work,

212 - .get_phys_page_debug = rx_cpu_get_phys_page_debug,

212 + .get_phys_addr_debug = rx_cpu_get_phys_addr_debug,

213 };

214

215 static const TCGCPUOps rx_tcg_ops = {

target/rx/cpu.h

+1 -1

@@ -136,7 +136,7 @@ struct RXCPUClass {

136 const char *rx_crname(uint8_t cr);

137 void rx_cpu_do_interrupt(CPUState *cpu);

138 bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);

139 -hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

139 +hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

140 void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

141 int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);

142 int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

target/rx/helper.c

+1 -1

@@ -147,7 +147,7 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

147 return false;

148 }

149

150 -hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

150 +hwaddr rx_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

151 {

152 return addr;

153 }

target/s390x/cpu-system.c

+1 -1

@@ -176,7 +176,7 @@ void s390_cpu_finalize(Object *obj)

176

177 static const struct SysemuCPUOps s390_sysemu_ops = {

178 .has_work = s390_cpu_has_work,

179 - .get_phys_page_debug = s390_cpu_get_phys_addr_debug,

179 + .get_phys_addr_debug = s390_cpu_get_phys_addr_debug,

180 .get_crash_info = s390_cpu_get_crash_info,

181 .write_elf64_note = s390_cpu_write_elf64_note,

182 .legacy_vmsd = &vmstate_s390_cpu,

target/sh4/cpu.c

+1 -1

@@ -278,7 +278,7 @@ static const VMStateDescription vmstate_sh_cpu = {

278

279 static const struct SysemuCPUOps sh4_sysemu_ops = {

280 .has_work = superh_cpu_has_work,

281 - .get_phys_page_debug = superh_cpu_get_phys_page_debug,

281 + .get_phys_addr_debug = superh_cpu_get_phys_addr_debug,

282 };

283 #endif

284

target/sh4/cpu.h

+1 -1

@@ -251,7 +251,7 @@ void sh4_translate_code(CPUState *cs, TranslationBlock *tb,

251 int *max_insns, vaddr pc, void *host_pc);

252

253 #if !defined(CONFIG_USER_ONLY)

254 -hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

254 +hwaddr superh_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

255 bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

256 MMUAccessType access_type, int mmu_idx,

257 bool probe, uintptr_t retaddr);

target/sh4/helper.c

+1 -1

@@ -435,7 +435,7 @@ static int get_physical_address(CPUSH4State *env, hwaddr* physical,

435 return get_mmu_address(env, physical, prot, address, access_type);

436 }

437

438 -hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

438 +hwaddr superh_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

439 {

440 hwaddr physical;

441 int prot;

target/sparc/cpu.c

+1 -1

@@ -1013,7 +1013,7 @@ static const MonitorDef sparc64_monitor_defs[] = {

1013

1014 static const struct SysemuCPUOps sparc_sysemu_ops = {

1015 .has_work = sparc_cpu_has_work,

1016 - .get_phys_page_debug = sparc_cpu_get_phys_page_debug,

1016 + .get_phys_addr_debug = sparc_cpu_get_phys_addr_debug,

1017 .legacy_vmsd = &vmstate_sparc_cpu,

1018 #if defined(TARGET_SPARC64)

1019 .monitor_defs = sparc64_monitor_defs,

target/sparc/cpu.h

+1 -1

@@ -580,7 +580,7 @@ struct SPARCCPUClass {

580 #ifndef CONFIG_USER_ONLY

581 extern const VMStateDescription vmstate_sparc_cpu;

582

583 -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

583 +hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

584 #endif

585

586 void sparc_cpu_do_interrupt(CPUState *cpu);

target/sparc/mmu_helper.c

+1 -1

@@ -902,7 +902,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,

902 }

903 #endif

904

905 -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

905 +hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

906 {

907 CPUSPARCState *env = cpu_env(cs);

908 hwaddr phys_addr;

target/tricore/cpu.c

+1 -1

@@ -176,7 +176,7 @@ static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request)

176

177 static const struct SysemuCPUOps tricore_sysemu_ops = {

178 .has_work = tricore_cpu_has_work,

179 - .get_phys_page_debug = tricore_cpu_get_phys_page_debug,

179 + .get_phys_addr_debug = tricore_cpu_get_phys_addr_debug,

180 };

181

182 static const TCGCPUOps tricore_tcg_ops = {

target/tricore/cpu.h

+1 -1

@@ -79,7 +79,7 @@ struct TriCoreCPUClass {

79 ResettablePhases parent_phases;

80 };

82 -hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

82 +hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

83 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

85 FIELD(PCXI, PCPN_13, 24, 8)

target/tricore/helper.c

+1 -1

@@ -46,7 +46,7 @@ static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,

46 return ret;

47 }

49 -hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

49 +hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

50 {

51 TriCoreCPU *cpu = TRICORE_CPU(cs);

52 hwaddr phys_addr;

target/xtensa/cpu.c

+1 -1

@@ -304,7 +304,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {

304

305 static const struct SysemuCPUOps xtensa_sysemu_ops = {

306 .has_work = xtensa_cpu_has_work,

307 - .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,

307 + .get_phys_addr_debug = xtensa_cpu_get_phys_addr_debug,

308 };

309 #endif

310

target/xtensa/cpu.h

+1 -1

@@ -590,7 +590,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,

590 unsigned size, MMUAccessType access_type,

591 int mmu_idx, MemTxAttrs attrs,

592 MemTxResult response, uintptr_t retaddr);

593 -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

593 +hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);

594 bool xtensa_debug_check_breakpoint(CPUState *cs);

595 #endif

596 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

target/xtensa/mmu_helper.c

+1 -1

@@ -316,7 +316,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,

316 }

317 }

318

319 -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)

319 +hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)

320 {

321 XtensaCPU *cpu = XTENSA_CPU(cs);

322 uint32_t paddr;