target/arm: GICv5 cpuif: Fix overflow in left shift
Coverity points out that we forgot the "ULL" suffix when shifting 1 right by a bitcount in various places, so for bit counts above 31 we end up shifting off the end of the word. Fix the three problems Coverity noticed and one more of the same kind that it didn't. CID: 1659588, 1659591, 1659559 Fixes: ce245ac6957 ("target/arm: GICv5 cpuif: Calculate the highest priority PPI") Fixes: 3f79212abae ("target/arm: GICv5 cpuif: Implement GICR CDIA command") Fixes: 49f4c98648c ("target/arm: GICv5 cpuif: Implement GIC CDDI") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260512093856.3197700-2-peter.maydell@linaro.org
Peter Maydell committed
May 12, 2026 at 10:38 UTC
883cd84e8211f7cd0a8a954e57044d23c707f004
1 file changed
+4
-4
target/arm/tcg/gicv5-cpuif.c
+4
-4
@@ -275,7 +275,7 @@ static void gic_recalc_ppi_hppi(CPUARMState *env)
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int ppi;
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int bit = ctz64(en_pend_nact);
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- en_pend_nact &= ~(1 << bit);
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+ en_pend_nact &= ~(1ULL << bit);
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ppi = i * 64 + bit;
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prio = extract64(env->gicv5_cpuif.ppi_priority[ppi / 8],
@@ -631,7 +631,7 @@ static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri)
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* gicv5_activate() cause a re-evaluation of HPPIs they use the
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* right (new) running priority.
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*/
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- env->gicv5_cpuif.icc_apr[domain] |= (1 << hppi.prio);
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+ env->gicv5_cpuif.icc_apr[domain] |= (1ULL << hppi.prio);
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switch (type) {
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case GICV5_PPI:
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{
@@ -639,7 +639,7 @@ static uint64_t gicr_cdia_read(CPUARMState *env, const ARMCPRegInfo *ri)
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assert(id < GICV5_NUM_PPIS);
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ppireg = id / 64;
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- ppibit = 1 << (id % 64);
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+ ppibit = 1ULL << (id % 64);
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env->gicv5_cpuif.ppi_active[ppireg] |= ppibit;
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if (!(env->gicv5_cpuif.ppi_hm[ppireg] & ppibit)) {
@@ -707,7 +707,7 @@ static void gic_cddi_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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ppireg = id / 64;
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- ppibit = 1 << (id % 64);
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+ ppibit = 1ULL << (id % 64);
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env->gicv5_cpuif.ppi_active[ppireg] &= ~ppibit;
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gic_recalc_ppi_hppi(env);