@samitouri / QOSamiQemu / commits / 88cca2edfc

ppc/pnv: Handle stash command in PowerNV SBE

Earlier since the SBE_CMD_STASH_MPIPL_CONFIG command was not handled, so skiboot used to not get any response from SBE: [ 106.350742821,3] SBE: Message timeout [chip id = 0], cmd = d7, subcmd = 7 [ 106.352067746,3] SBE: Failed to send stash MPIPL config [chip id = 0x0, rc = 254] Fix this by handling the command in PowerNV SBE, and sending a response so skiboot knows SBE has handled the STASH command The stashed skiboot base is later used to access the relocated MDST/MDDT tables when MPIPL is implemented. The purpose of stashing relocated base address is explained in following skiboot commit: author Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Fri Jul 12 16:47:51 2019 +0530 committer Oliver O'Halloran <oohall@gmail.com> Thu Aug 15 17:53:39 2019 +1000 SBE: Send OPAL relocated base address to SBE OPAL relocates itself during boot. During memory preserving IPL hostboot needs to access relocated OPAL base address to get MDST, MDDT tables. Hence send relocated base address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send stashed data to hostboot... so that hostboot can access these data. Reviewed-by: Hari Bathini <hbathini@linux.ibm.com> Reviewed-by: Sourabh Jain <sourabhjain@linux.ibm.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Shivang Upadhyay <shivangu@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260424083837.214947-4-adityag@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>

Aditya Gupta committed Apr 24, 2026 at 14:08 UTC 88cca2edfc186cc12168f87244942315263f950e
2 files changed +43
hw/ppc/pnv_sbe.c
+38
@@ -233,8 +233,11 @@ static void sbe_timer(void *opaque)
233
234 static void do_sbe_msg(PnvSBE *sbe)
235 {
236 + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
237 + MachineState *machine = MACHINE(pnv);
238 struct sbe_msg msg;
239 uint16_t cmd, ctrl_flags, seq_id;
240 + uint64_t mbox_val;
241 int i;
242
243 memset(&msg, 0, sizeof(msg));
@@ -265,6 +268,41 @@ static void do_sbe_msg(PnvSBE *sbe)
268 timer_del(sbe->timer);
269 }
270 break;
271 + case SBE_CMD_STASH_MPIPL_CONFIG:
272 + /* key = sbe->mbox[1] */
273 + switch (sbe->mbox[1]) {
274 + case SBE_STASH_KEY_SKIBOOT_BASE:
275 + mbox_val = sbe->mbox[2];
276 + if (mbox_val >= machine->ram_size) {
277 + qemu_log_mask(LOG_GUEST_ERROR,
278 + "SBE: skiboot_base 0x%" PRIx64 \
279 + "exceeds RAM size 0x" RAM_ADDR_FMT "\n",
280 + mbox_val, machine->ram_size);
281 + return;
282 + }
283 +
284 + pnv->mpipl_state.skiboot_base = mbox_val;
285 + qemu_log_mask(LOG_UNIMP,
286 + "Stashing skiboot base: 0x%" HWADDR_PRIx "\n",
287 + pnv->mpipl_state.skiboot_base);
288 +
289 + /*
290 + * Set the response register.
291 + *
292 + * Currently setting the same sequence number in
293 + * response as we got in the request.
294 + */
295 + sbe->mbox[4] = sbe->mbox[0]; /* sequence number */
296 + pnv_sbe_set_host_doorbell(sbe,
297 + sbe->host_doorbell | SBE_HOST_RESPONSE_WAITING);
298 +
299 + break;
300 + default:
301 + qemu_log_mask(LOG_UNIMP,
302 + "SBE: CMD_STASH_MPIPL_CONFIG: Unimplemented key: 0x" TARGET_FMT_lx "\n",
303 + sbe->mbox[1]);
304 + }
305 + break;
306 default:
307 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd);
308 }
include/hw/ppc/pnv_mpipl.h
+5
@@ -8,11 +8,16 @@
8 #define PNV_MPIPL_H
9
10 #include <stdbool.h>
11 +#include <stdint.h>
12 +
13 +#include "exec/hwaddr.h"
14
15 typedef struct MpiplPreservedState MpiplPreservedState;
16
17 /* Preserved state to be saved in PnvMachineState */
18 struct MpiplPreservedState {
19 + /* skiboot_base will be valid only after OPAL sends relocated base to SBE */
20 + hwaddr skiboot_base;
21 bool is_next_boot_mpipl;
22 };
23