target/arm: migrate BXJ trap syndromes to registerfields
This is an Armv7 specific syndrome for chips with Jazelle functionality. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-9-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
899ffd01131b42cd45de4f8c72f912589f502f9a
1 file changed
+18
-2
target/arm/syndrome.h
+18
-2
@@ -440,10 +440,26 @@ static inline uint32_t syn_btitrap(int btype)
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return res;
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}
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+/*
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+ * ISS encoding for trapped BXJ execution
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+ *
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+ * This is an Armv7 encoding.
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+ */
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+FIELD(BXJ_ISS, RM, 0, 4)
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+/* bits 4:19 are Reserved, UNK/SBZP */
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+FIELD(BXJ_ISS, COND, 20, 4)
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+FIELD(BXJ_ISS, CV, 24, 1)
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+
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static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
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{
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- return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
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- (cv << 24) | (cond << 20) | rm;
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+ uint32_t res = syn_set_ec(0, EC_BXJTRAP);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, BXJ_ISS, CV, cv);
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+ res = FIELD_DP32(res, BXJ_ISS, COND, cond);
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+ res = FIELD_DP32(res, BXJ_ISS, RM, rm);
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+
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+ return res;
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}
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static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,