target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR
Replace the same vill reset flow by reset_ill_vtype function. Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Max Chou committed
Apr 2, 2026 at 20:52 UTC
8a9da8305e9b592aa72974af004a18b6a6665271
1 file changed
+11
-10
target/riscv/vector_helper.c
+11
-10
@@ -49,6 +49,15 @@ static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)
49
return reserved;
50
}
51
52
+static inline void reset_ill_vtype(CPURISCVState *env)
53
+{
54
+ /* only set vill bit. */
55
+ env->vill = 1;
56
+ env->vtype = 0;
57
+ env->vl = 0;
58
+ env->vstart = 0;
59
+}
60
+
61
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
62
target_ulong s2, target_ulong x0)
63
{
@@ -93,11 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
102
}
103
104
if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {
96
- /* only set vill bit. */
97
- env->vill = 1;
98
- env->vtype = 0;
99
- env->vl = 0;
100
- env->vstart = 0;
105
+ reset_ill_vtype(env);
106
return 0;
107
}
108
@@ -113,11 +118,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
118
}
119
120
if (cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl != vl)) {
116
- /* only set vill bit. */
117
- env->vill = 1;
118
- env->vtype = 0;
119
- env->vl = 0;
120
- env->vstart = 0;
121
+ reset_ill_vtype(env);
122
return 0;
123
}
124