@samitouri / QOSamiQemu / commits / 92ca187a30

target/arm: hvf: add asserts for code paths not leveraged when using the vGIC

When using the vGIC, timers are directly handled by the platform. No vmexits ought to happen in that case. Abort if reaching those code paths. Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260429190532.26538-10-mohamed@unpredictable.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Mohamed Mediouni committed May 5, 2026 at 09:25 UTC 92ca187a30929f78d1baf9fd8ed7ff4570965399

1 file changed +3

target/arm/hvf/hvf.c

@@ -1696,6 +1696,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)

1696 case SYSREG_ICC_SGI1R_EL1:

1697 case SYSREG_ICC_SRE_EL1:

1698 case SYSREG_ICC_CTLR_EL1:

1699 + assert(!hvf_irqchip_in_kernel());

1700 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */

1701 if (hvf_sysreg_read_cp(cpu, "GICv3", reg, val)) {

1702 return 0;

@@ -1986,6 +1987,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)

1987 case SYSREG_ICC_SGI0R_EL1:

1988 case SYSREG_ICC_SGI1R_EL1:

1989 case SYSREG_ICC_SRE_EL1:

1990 + assert(!hvf_irqchip_in_kernel());

1991 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */

1992 if (hvf_sysreg_write_cp(cpu, "GICv3", reg, val)) {

1993 return 0;

@@ -2393,6 +2395,7 @@ static int hvf_handle_vmexit(CPUState *cpu, hv_vcpu_exit_t *exit)

2395 ret = hvf_handle_exception(cpu, &exit->exception);

2396 break;

2397 case HV_EXIT_REASON_VTIMER_ACTIVATED:

2398 + assert(!hvf_irqchip_in_kernel());

2399 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);

2400 cpu->accel->vtimer_masked = true;

2401 break;