target/mips: add Octeon LHUX instruction
LHUX performs an indexed unsigned halfword load from base + index and zero-extends the result into rd. Add the decode entry and reuse the common indexed-load translator with MO_UW. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-12-philmd@linaro.org>
James Hilliard committed
May 8, 2026 at 10:50 UTC
932726ee8a9de91982bc6b9eb9413faa9a5c0aa2
2 files changed
+2
target/mips/tcg/octeon.decode
+1
@@ -48,6 +48,7 @@ SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi
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@lx ...... base:5 index:5 rd:5 ...... ..... &lx
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LWX 011111 ..... ..... ..... 00000 001010 @lx
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LHX 011111 ..... ..... ..... 00100 001010 @lx
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+LHUX 011111 ..... ..... ..... 10100 001010 @lx
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LBUX 011111 ..... ..... ..... 00110 001010 @lx
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LBX 011111 ..... ..... ..... 10110 001010 @lx
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LDX 011111 ..... ..... ..... 01000 001010 @lx
target/mips/tcg/octeon_translate.c
+1
@@ -164,5 +164,6 @@ static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
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TRANS(LBX, trans_lx, MO_SB);
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TRANS(LBUX, trans_lx, MO_UB);
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TRANS(LHX, trans_lx, MO_SW);
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+TRANS(LHUX, trans_lx, MO_UW);
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TRANS(LWX, trans_lx, MO_SL);
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TRANS(LDX, trans_lx, MO_UQ);