hw/arm/fsl-imx8mm: Adding support for General Purpose Timers
It enables emulation of GPT in iMX8MM Added GPT IRQ lines Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gaurav Sharma committed
Apr 21, 2026 at 12:22 UTC
9446f60d99bef25b23a9621cf01065b896ee6a17
5 files changed
+94
hw/arm/Kconfig
+1
@@ -626,6 +626,7 @@ config FSL_IMX8MM
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select FSL_IMX8MP_CCM
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select IMX
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select IMX_I2C
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+ select OR_IRQ
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select SDHCI
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select PCI_EXPRESS_DESIGNWARE
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select PCI_EXPRESS_FSL_IMX8M_PHY
hw/arm/fsl-imx8mm.c
+54
@@ -180,6 +180,13 @@ static void fsl_imx8mm_init(Object *obj)
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object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
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}
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+ for (i = 0; i < FSL_IMX8MM_NUM_GPTS; i++) {
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+ g_autofree char *name = g_strdup_printf("gpt%d", i + 1);
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+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MM_GPT);
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+ }
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+ object_initialize_child(obj, "gpt5-gpt6-irq", &s->gpt5_gpt6_irq,
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+ TYPE_OR_IRQ);
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+
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for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {
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g_autofree char *name = g_strdup_printf("i2c%d", i + 1);
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object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
@@ -385,6 +392,52 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr,
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&s->ocram);
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+ /* GPTs */
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+ object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), "num-lines", 2,
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+ &error_abort);
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+ if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) {
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+ return;
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+ }
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+
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+ qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0,
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+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_GPT5_GPT6_IRQ));
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+
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+ for (i = 0; i < FSL_IMX8MM_NUM_GPTS; i++) {
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+ hwaddr gpt_addrs[FSL_IMX8MM_NUM_GPTS] = {
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT1].addr,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT2].addr,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT3].addr,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT4].addr,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT5].addr,
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+ fsl_imx8mm_memmap[FSL_IMX8MM_GPT6].addr,
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+ };
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+
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+ s->gpt[i].ccm = IMX_CCM(&s->ccm);
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+
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+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) {
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+ return;
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+ }
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+
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+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]);
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+
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+ if (i < FSL_IMX8MM_NUM_GPTS - 2) {
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+ static const unsigned int gpt_irqs[FSL_IMX8MM_NUM_GPTS - 2] = {
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+ FSL_IMX8MM_GPT1_IRQ,
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+ FSL_IMX8MM_GPT2_IRQ,
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+ FSL_IMX8MM_GPT3_IRQ,
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+ FSL_IMX8MM_GPT4_IRQ,
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+ };
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+
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
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+ qdev_get_gpio_in(gicdev, gpt_irqs[i]));
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+ } else {
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+ int irq = i - FSL_IMX8MM_NUM_GPTS + 2;
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+
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+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
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+ qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq), irq));
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+ }
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+ }
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+
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/* I2Cs */
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for (i = 0; i < FSL_IMX8MM_NUM_I2CS; i++) {
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static const struct {
@@ -555,6 +608,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
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case FSL_IMX8MM_GIC_DIST:
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case FSL_IMX8MM_GIC_REDIST:
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case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:
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+ case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6:
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case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:
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case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:
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case FSL_IMX8MM_PCIE1:
hw/timer/imx_gpt.c
+26
@@ -6,6 +6,7 @@
6
* Originally written by Hans Jiang
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* Updated by Peter Chubb
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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+ * Updated by Gaurav Sharma <gaurav.sharma_7@nxp.com>
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
@@ -137,6 +138,17 @@ static const IMXClk imx8mp_gpt_clocks[] = {
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CLK_NONE, /* 111 not defined */
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};
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+static const IMXClk imx8mm_gpt_clocks[] = {
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+ CLK_NONE, /* 000 No clock source */
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+ CLK_IPG, /* 001 ipg_clk, 532MHz */
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+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
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+ CLK_EXT, /* 011 External clock */
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+ CLK_32k, /* 100 ipg_clk_32k */
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+ CLK_HIGH, /* 101 ipg_clk_16M */
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+ CLK_NONE, /* 110 not defined */
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+ CLK_NONE, /* 111 not defined */
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+};
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+
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/* Must be called from within ptimer_transaction_begin/commit block */
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static void imx_gpt_set_freq(IMXGPTState *s)
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{
@@ -570,6 +582,13 @@ static void imx8mp_gpt_init(Object *obj)
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s->clocks = imx8mp_gpt_clocks;
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}
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+static void imx8mm_gpt_init(Object *obj)
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+{
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+ IMXGPTState *s = IMX_GPT(obj);
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+
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+ s->clocks = imx8mm_gpt_clocks;
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+}
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+
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static const TypeInfo imx25_gpt_info = {
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.name = TYPE_IMX25_GPT,
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.parent = TYPE_SYS_BUS_DEVICE,
@@ -608,6 +627,12 @@ static const TypeInfo imx8mp_gpt_info = {
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.instance_init = imx8mp_gpt_init,
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};
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+static const TypeInfo imx8mm_gpt_info = {
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+ .name = TYPE_IMX8MM_GPT,
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+ .parent = TYPE_IMX25_GPT,
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+ .instance_init = imx8mm_gpt_init,
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+};
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+
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static void imx_gpt_register_types(void)
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{
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type_register_static(&imx25_gpt_info);
@@ -616,6 +641,7 @@ static void imx_gpt_register_types(void)
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type_register_static(&imx6ul_gpt_info);
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type_register_static(&imx7_gpt_info);
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type_register_static(&imx8mp_gpt_info);
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+ type_register_static(&imx8mm_gpt_info);
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}
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type_init(imx_gpt_register_types)
include/hw/arm/fsl-imx8mm.h
+11
@@ -18,10 +18,12 @@
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#include "hw/misc/imx7_snvs.h"
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#include "hw/misc/imx8mp_analog.h"
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#include "hw/misc/imx8mp_ccm.h"
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+#include "hw/or-irq.h"
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#include "hw/pci-host/designware.h"
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#include "hw/pci-host/fsl_imx8m_phy.h"
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#include "hw/sd/sdhci.h"
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#include "hw/ssi/imx_spi.h"
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+#include "hw/timer/imx_gpt.h"
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#include "hw/watchdog/wdt_imx2.h"
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#include "qom/object.h"
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#include "qemu/units.h"
@@ -36,6 +38,7 @@ enum FslImx8mmConfiguration {
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FSL_IMX8MM_NUM_CPUS = 4,
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FSL_IMX8MM_NUM_ECSPIS = 3,
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FSL_IMX8MM_NUM_GPIOS = 5,
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+ FSL_IMX8MM_NUM_GPTS = 6,
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FSL_IMX8MM_NUM_I2CS = 4,
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FSL_IMX8MM_NUM_IRQS = 128,
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FSL_IMX8MM_NUM_UARTS = 4,
@@ -48,6 +51,7 @@ struct FslImx8mmState {
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ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];
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GICv3State gic;
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+ IMXGPTState gpt[FSL_IMX8MM_NUM_GPTS];
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IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];
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IMX8MPCCMState ccm;
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IMX8MPAnalogState analog;
@@ -60,6 +64,7 @@ struct FslImx8mmState {
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IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];
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DesignwarePCIEHost pcie;
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FslImx8mPciePhyState pcie_phy;
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+ OrIRQState gpt5_gpt6_irq;
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};
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enum FslImx8mmMemoryRegions {
@@ -192,6 +197,12 @@ enum FslImx8mmIrqs {
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FSL_IMX8MM_I2C3_IRQ = 37,
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FSL_IMX8MM_I2C4_IRQ = 38,
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+ FSL_IMX8MM_GPT1_IRQ = 55,
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+ FSL_IMX8MM_GPT2_IRQ = 54,
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+ FSL_IMX8MM_GPT3_IRQ = 53,
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+ FSL_IMX8MM_GPT4_IRQ = 52,
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+ FSL_IMX8MM_GPT5_GPT6_IRQ = 51,
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+
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FSL_IMX8MM_GPIO1_LOW_IRQ = 64,
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FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,
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FSL_IMX8MM_GPIO2_LOW_IRQ = 66,
include/hw/timer/imx_gpt.h
+2
@@ -6,6 +6,7 @@
6
* Originally written by Hans Jiang
7
* Updated by Peter Chubb
8
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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+ * Updated by Gaurav Sharma <gaurav.sharma_7@nxp.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
@@ -81,6 +82,7 @@
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#define TYPE_IMX6UL_GPT "imx6ul.gpt"
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#define TYPE_IMX7_GPT "imx7.gpt"
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#define TYPE_IMX8MP_GPT "imx8mp.gpt"
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+#define TYPE_IMX8MM_GPT "imx8mm.gpt"
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#define TYPE_IMX_GPT TYPE_IMX25_GPT
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