hw/cxl/events: Updates for rev3.2 DRAM event record
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record has updated with following new fields. 1. Component Identifier 2. Sub-channel of the memory event location 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Volatile Memory Error Count at Event 5. Memory Event Sub-Type Add updates for the above spec changes in the CXL DRAM event reporting and QMP command to inject DRAM event. In order to ensure consistency update all specification references for this command to CXL r3.2. Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20260205112350.60681-5-Jonathan.Cameron@huawei.com>
Shiju Jose committed
Feb 5, 2026 at 11:23 UTC
94976b8631a11297b52826f51a638242b2767f9f
4 files changed
+83
-10
hw/mem/cxl_type3.c
+43
-1
@@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
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#define CXL_DRAM_VALID_ROW BIT(5)
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#define CXL_DRAM_VALID_COLUMN BIT(6)
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#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
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+#define CXL_DRAM_VALID_COMPONENT BIT(8)
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+#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9)
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+#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10)
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+
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+#define CXL_DRAM_EV_DESC_UCE BIT(0)
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+#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1)
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+#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
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void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
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uint32_t flags,
@@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
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bool has_column, uint16_t column,
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bool has_correction_mask,
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uint64List *correction_mask,
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+ const char *component_id,
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+ bool has_comp_id_pldm, bool is_comp_id_pldm,
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+ bool has_sub_channel, uint8_t sub_channel,
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+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
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+ bool has_cvme_count, uint32_t cvme_count,
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+ uint8_t sub_type,
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Error **errp)
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{
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Object *obj = object_resolve_path(path, NULL);
@@ -1838,7 +1851,6 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
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has_maint_op_subclass, maint_op_subclass,
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has_ld_id, ld_id, has_head_id, head_id);
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stq_le_p(&dram.phys_addr, dpa);
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- dram.descriptor = descriptor;
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dram.type = type;
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dram.transaction_type = transaction_type;
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@@ -1888,6 +1900,36 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
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valid_flags |= CXL_DRAM_VALID_CORRECTION_MASK;
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}
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+ if (component_id) {
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+ strncpy((char *)dram.component_id, component_id,
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+ sizeof(dram.component_id) - 1);
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+ valid_flags |= CXL_DRAM_VALID_COMPONENT;
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+ if (has_comp_id_pldm && is_comp_id_pldm) {
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+ valid_flags |= CXL_DRAM_VALID_COMPONENT_ID_FORMAT;
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+ }
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+ }
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+
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+ if (has_sub_channel) {
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+ dram.sub_channel = sub_channel;
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+ valid_flags |= CXL_DRAM_VALID_SUB_CHANNEL;
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+ }
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+
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+ if (has_cme_ev_flags) {
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+ dram.cme_ev_flags = cme_ev_flags;
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+ } else {
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+ dram.cme_ev_flags = 0;
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+ }
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+
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+ if (has_cvme_count) {
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+ descriptor |= CXL_DRAM_EV_DESC_THRESHOLD_EVENT;
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+ st24_le_p(dram.cvme_count, cvme_count);
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+ } else {
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+ st24_le_p(dram.cvme_count, 0);
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+ }
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+ dram.descriptor = descriptor;
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+
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+ dram.sub_type = sub_type;
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+
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stw_le_p(&dram.validity_flags, valid_flags);
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if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
hw/mem/cxl_type3_stubs.c
+7
@@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
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bool has_column, uint16_t column,
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bool has_correction_mask,
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uint64List *correction_mask,
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+ const char *component_id,
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+ bool has_comp_id_pldm,
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+ bool is_comp_id_pldm,
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+ bool has_sub_channel, uint8_t sub_channel,
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+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
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+ bool has_cvme_count, uint32_t cvme_count,
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+ uint8_t sub_type,
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Error **errp) {}
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void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
include/hw/cxl/cxl_events.h
+7
-2
@@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia {
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/*
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* DRAM Event Record
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- * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46
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+ * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
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* All fields little endian.
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*/
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typedef struct CXLEventDram {
@@ -156,7 +156,12 @@ typedef struct CXLEventDram {
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uint8_t row[3];
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uint16_t column;
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uint64_t correction_mask[4];
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- uint8_t reserved[0x17];
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+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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+ uint8_t sub_channel;
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+ uint8_t cme_ev_flags;
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+ uint8_t cvme_count[3];
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+ uint8_t sub_type;
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+ uint8_t reserved;
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} QEMU_PACKED CXLEventDram;
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/*
qapi/cxl.json
+26
-7
@@ -131,21 +131,21 @@
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##
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# @CXLDRAMEvent:
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#
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-# Event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
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+# Event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
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#
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# @dpa: Device Physical Address (relative to @path device). Note
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-# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
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+# lower bits include some flags. See CXL r3.2 Table 8-58 DRAM
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# Event Record, Physical Address.
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#
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# @descriptor: Memory Event Descriptor with additional memory event
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-# information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
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+# information. See CXL r3.2 Table 8-58 DRAM Event Record, Memory
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# Event Descriptor for bit definitions.
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#
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-# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44
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+# @type: Type of memory event that occurred. See CXL r3.2 Table 8-58
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# DRAM Event Record, Memory Event Type for possible values.
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#
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# @transaction-type: Type of first transaction that caused the event
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-# to occur. See CXL r3.0 Table 8-44 DRAM Event Record,
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+# to occur. See CXL r3.2 Table 8-58 DRAM Event Record,
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# Transaction Type for possible values.
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#
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# @channel: The channel of the memory event location. A channel is an
@@ -169,6 +169,21 @@
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# @correction-mask: Bits within each nibble. Used in order of bits
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# set in the nibble-mask. Up to 4 nibbles may be covered.
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#
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+# @component-id: Device specific component identifier for the event.
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+# May describe a field replaceable sub-component of the device.
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+#
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+# @is-comp-id-pldm: This flag specifies whether the device-specific
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+# component identifier format follows PLDM.
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+#
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+# @sub-channel: The sub-channel of the memory event location.
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+#
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+# @cme-ev-flags: Advanced programmable corrected memory error
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+# threshold event flags.
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+#
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+# @cvme-count: Corrected volatile memory error count at event.
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+#
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+# @sub-type: Memory event sub-type.
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+#
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# Since: 8.1
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##
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{ 'struct': 'CXLDRAMEvent',
@@ -177,13 +192,17 @@
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'type': 'uint8', 'transaction-type': 'uint8',
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'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
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'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
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- '*column': 'uint16', '*correction-mask': [ 'uint64' ]
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+ '*column': 'uint16', '*correction-mask': [ 'uint64' ],
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+ '*component-id': 'str', '*is-comp-id-pldm':'bool',
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+ '*sub-channel':'uint8',
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+ '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
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+ 'sub-type':'uint8'
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}}
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##
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# @cxl-inject-dram-event:
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#
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-# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
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+# Inject an event record for a DRAM Event (CXL r3.2 8.2.10.2.1.2).
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# This event type is reported via one of the event logs
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# specified via the log parameter.
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#