hw/intc/arm_gicv5: Define macros for config frame registers
Define constants for the various registers in the IRS config frame using the REG and FIELD macros. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-10-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
958d84e437f99e581903f83596a6387af88af0df
1 file changed
+243
hw/intc/arm_gicv5.c
+243
@@ -7,6 +7,7 @@
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*/
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#include "qemu/osdep.h"
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+#include "hw/core/registerfields.h"
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#include "hw/intc/arm_gicv5.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
@@ -22,6 +23,248 @@ static const char *domain_name[] = {
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[GICV5_ID_REALM] = "Realm",
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};
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+REG32(IRS_IDR0, 0x0)
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+ FIELD(IRS_IDR0, INT_DOM, 0, 2)
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+ FIELD(IRS_IDR0, PA_RANGE, 2, 4)
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+ FIELD(IRS_IDR0, VIRT, 6, 1)
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+ FIELD(IRS_IDR0, ONE_N, 7, 1)
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+ FIELD(IRS_IDR0, VIRT_ONE_N, 8, 1)
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+ FIELD(IRS_IDR0, SETLPI, 9, 1)
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+ FIELD(IRS_IDR0, MEC, 10, 1)
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+ FIELD(IRS_IDR0, MPAM, 11, 1)
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+ FIELD(IRS_IDR0, SWE, 12, 1)
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+ FIELD(IRS_IDR0, IRSID, 16, 16)
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+
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+REG32(IRS_IDR1, 0x4)
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+ FIELD(IRS_IDR1, PE_CNT, 0, 16)
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+ FIELD(IRS_IDR1, IAFFID_BITS, 16, 4)
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+ FIELD(IRS_IDR1, PRI_BITS, 20, 3)
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+
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+REG32(IRS_IDR2, 0x8)
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+ FIELD(IRS_IDR2, ID_BITS, 0, 5)
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+ FIELD(IRS_IDR2, LPI, 5, 1)
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+ FIELD(IRS_IDR2, MIN_LPI_ID_BITS, 6, 4)
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+ FIELD(IRS_IDR2, IST_LEVELS, 10, 1)
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+ FIELD(IRS_IDR2, IST_L2SZ, 11, 3)
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+ FIELD(IRS_IDR2, IST_MD, 14, 1)
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+ FIELD(IRS_IDR2, ISTMD_SZ, 15, 5)
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+
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+REG32(IRS_IDR3, 0xc)
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+ FIELD(IRS_IDR3, VMD, 0, 1)
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+ FIELD(IRS_IDR3, VMD_SZ, 1, 4)
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+ FIELD(IRS_IDR3, VM_ID_BITS, 5, 5)
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+ FIELD(IRS_IDR3, VMT_LEVELS, 10, 1)
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+
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+REG32(IRS_IDR4, 0x10)
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+ FIELD(IRS_IDR4, VPED_SZ, 0, 6)
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+ FIELD(IRS_IDR4, VPE_ID_BITS, 6, 4)
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+
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+REG32(IRS_IDR5, 0x14)
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+ FIELD(IRS_IDR5, SPI_RANGE, 0, 25)
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+
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+REG32(IRS_IDR6, 0x18)
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+ FIELD(IRS_IDR6, SPI_IRS_RANGE, 0, 25)
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+
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+REG32(IRS_IDR7, 0x1c)
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+ FIELD(IRS_IDR7, SPI_BASE, 0, 24)
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+
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+REG32(IRS_IIDR, 0x40)
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+ FIELD(IRS_IIDR, IMPLEMENTER, 0, 12)
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+ FIELD(IRS_IIDR, REVISION, 12, 4)
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+ FIELD(IRS_IIDR, VARIANT, 16, 4)
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+ FIELD(IRS_IIDR, PRODUCTID, 20, 12)
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+
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+REG32(IRS_AIDR, 0x44)
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+ FIELD(IRS_AIDR, ARCHMINORREV, 0, 4)
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+ FIELD(IRS_AIDR, ARCHMAJORREV, 4, 4)
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+ FIELD(IRS_AIDR, COMPONENT, 8, 4)
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+
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+REG32(IRS_CR0, 0x80)
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+ FIELD(IRS_CR0, IRSEN, 0, 1)
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+ FIELD(IRS_CR0, IDLE, 1, 1)
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+
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+REG32(IRS_CR1, 0x84)
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+ FIELD(IRS_CR1, SH, 0, 2)
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+ FIELD(IRS_CR1, OC, 2, 2)
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+ FIELD(IRS_CR1, IC, 4, 2)
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+ FIELD(IRS_CR1, IST_RA, 6, 1)
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+ FIELD(IRS_CR1, IST_WA, 7, 1)
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+ FIELD(IRS_CR1, VMT_RA, 8, 1)
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+ FIELD(IRS_CR1, VMT_WA, 9, 1)
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+ FIELD(IRS_CR1, VPET_RA, 10, 1)
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+ FIELD(IRS_CR1, VPET_WA, 11, 1)
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+ FIELD(IRS_CR1, VMD_RA, 12, 1)
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+ FIELD(IRS_CR1, VMD_WA, 13, 1)
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+ FIELD(IRS_CR1, VPED_RA, 14, 1)
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+ FIELD(IRS_CR1, VPED_WA, 15, 1)
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+
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+REG32(IRS_SYNCR, 0xc0)
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+ FIELD(IRS_SYNCR, SYNC, 31, 1)
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+
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+REG32(IRS_SYNC_STATUSR, 0xc4)
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+ FIELD(IRS_SYNC_STATUSR, IDLE, 0, 1)
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+
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+REG64(IRS_SPI_VMR, 0x100)
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+ FIELD(IRS_SPI_VMR, VM_ID, 0, 16)
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+ FIELD(IRS_SPI_VMR, VIRT, 63, 1)
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+
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+REG32(IRS_SPI_SELR, 0x108)
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+ FIELD(IRS_SPI_SELR, ID, 0, 24)
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+
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+REG32(IRS_SPI_DOMAINR, 0x10c)
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+ FIELD(IRS_SPI_DOMAINR, DOMAIN, 0, 2)
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+
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+REG32(IRS_SPI_RESAMPLER, 0x110)
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+ FIELD(IRS_SPI_RESAMPLER, SPI_ID, 0, 24)
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+
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+REG32(IRS_SPI_CFGR, 0x114)
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+ FIELD(IRS_SPI_CFGR, TM, 0, 1)
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+
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+REG32(IRS_SPI_STATUSR, 0x118)
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+ FIELD(IRS_SPI_STATUSR, IDLE, 0, 1)
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+ FIELD(IRS_SPI_STATUSR, V, 1, 1)
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+
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+REG32(IRS_PE_SELR, 0x140)
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+ FIELD(IRS_PE_SELR, IAFFID, 0, 16)
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+
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+REG32(IRS_PE_STATUSR, 0x144)
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+ FIELD(IRS_PE_STATUSR, IDLE, 0, 1)
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+ FIELD(IRS_PE_STATUSR, V, 1, 1)
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+ FIELD(IRS_PE_STATUSR, ONLINE, 2, 1)
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+
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+REG32(IRS_PE_CR0, 0x148)
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+ FIELD(IRS_PE_CR0, DPS, 0, 1)
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+
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+REG64(IRS_IST_BASER, 0x180)
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+ FIELD(IRS_IST_BASER, VALID, 0, 1)
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+ FIELD(IRS_IST_BASER, ADDR, 6, 50)
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+
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+REG32(IRS_IST_CFGR, 0x190)
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+ FIELD(IRS_IST_CFGR, LPI_ID_BITS, 0, 5)
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+ FIELD(IRS_IST_CFGR, L2SZ, 5, 2)
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+ FIELD(IRS_IST_CFGR, ISTSZ, 7, 2)
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+ FIELD(IRS_IST_CFGR, STRUCTURE, 16, 1)
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+
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+REG32(IRS_IST_STATUSR, 0x194)
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+ FIELD(IRS_IST_STATUSR, IDLE, 0, 1)
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+
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+REG32(IRS_MAP_L2_ISTR, 0x1c0)
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+ FIELD(IRS_MAP_L2_ISTR, ID, 0, 24)
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+
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+REG64(IRS_VMT_BASER, 0x200)
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+ FIELD(IRS_VMT_BASER, VALID, 0, 1)
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+ FIELD(IRS_VMT_BASER, ADDR, 3, 53)
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+
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+REG32(IRS_VMT_CFGR, 0x210)
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+ FIELD(IRS_VMT_CFGR, VM_ID_BITS, 0, 5)
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+ FIELD(IRS_VMT_CFGR, STRUCTURE, 16, 1)
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+
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+REG32(IRS_VMT_STATUSR, 0x124)
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+ FIELD(IRS_VMT_STATUSR, IDLE, 0, 1)
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+
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+REG64(IRS_VPE_SELR, 0x240)
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+ FIELD(IRS_VPE_SELR, VM_ID, 0, 16)
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+ FIELD(IRS_VPE_SELR, VPE_ID, 32, 16)
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+ FIELD(IRS_VPE_SELR, S, 63, 1)
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+
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+REG64(IRS_VPE_DBR, 0x248)
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+ FIELD(IRS_VPE_DBR, INTID, 0, 24)
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+ FIELD(IRS_VPE_DBR, DBPM, 32, 5)
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+ FIELD(IRS_VPE_DBR, REQ_DB, 62, 1)
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+ FIELD(IRS_VPE_DBR, DBV, 63, 1)
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+
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+REG32(IRS_VPE_HPPIR, 0x250)
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+ FIELD(IRS_VPE_HPPIR, ID, 0, 24)
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+ FIELD(IRS_VPE_HPPIR, TYPE, 29, 3)
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+ FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1)
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+
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+REG32(IRS_VPE_CR0, 0x258)
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+ FIELD(IRS_VPE_CR0, DPS, 0, 1)
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+
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+REG32(IRS_VPE_STATUSR, 0x25c)
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+ FIELD(IRS_VPE_STATUSR, IDLE, 0, 1)
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+ FIELD(IRS_VPE_STATUSR, V, 1, 1)
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+
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+REG64(IRS_VM_DBR, 0x280)
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+ FIELD(IRS_VM_DBR, VPE_ID, 0, 16)
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+ FIELD(IRS_VM_DBR, EN, 63, 1)
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+
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+REG32(IRS_VM_SELR, 0x288)
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+ FIELD(IRS_VM_SELR, VM_ID, 0, 16)
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+
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+REG32(IRS_VM_STATUSR, 0x28c)
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+ FIELD(IRS_VM_STATUSR, IDLE, 0, 1)
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+ FIELD(IRS_VM_STATUSR, V, 1, 1)
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+
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+REG64(IRS_VMAP_L2_VMTR, 0x2c0)
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+ FIELD(IRS_VMAP_L2_VMTR, VM_ID, 0, 16)
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+ FIELD(IRS_VMAP_L2_VMTR, M, 63, 1)
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+
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+REG64(IRS_VMAP_VMR, 0x2c8)
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+ FIELD(IRS_VMAP_VMR, VM_ID, 0, 16)
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+ FIELD(IRS_VMAP_VMR, U, 62, 1)
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+ FIELD(IRS_VMAP_VMR, M, 63, 1)
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+
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+REG64(IRS_VMAP_VISTR, 0x2d0)
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+ FIELD(IRS_VMAP_VISTR, TYPE, 29, 3)
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+ FIELD(IRS_VMAP_VISTR, VM_ID, 32, 16)
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+ FIELD(IRS_VMAP_VISTR, U, 62, 1)
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+ FIELD(IRS_VMAP_VISTR, M, 63, 1)
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+
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+REG64(IRS_VMAP_L2_VISTR, 0x2d8)
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+ FIELD(IRS_VMAP_L2_VISTR, ID, 0, 24)
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+ FIELD(IRS_VMAP_L2_VISTR, TYPE, 29, 3)
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+ FIELD(IRS_VMAP_L2_VISTR, VM_ID, 32, 16)
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+ FIELD(IRS_VMAP_L2_VISTR, M, 63, 1)
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+
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+REG64(IRS_VMAP_VPER, 0x2e0)
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+ FIELD(IRS_VMAP_VPER, VPE_ID, 0, 16)
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+ FIELD(IRS_VMAP_VPER, VM_ID, 32, 16)
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+ FIELD(IRS_VMAP_VPER, M, 63, 1)
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+
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+REG64(IRS_SAVE_VMR, 0x300)
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+ FIELD(IRS_SAVE_VMR, VM_ID, 0, 16)
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+ FIELD(IRS_SAVE_VMR, Q, 62, 1)
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+ FIELD(IRS_SAVE_VMR, S, 63, 1)
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+
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+REG32(IRS_SAVE_VM_STATUSR, 0x308)
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+ FIELD(IRS_SAVE_VM_STATUSR, IDLE, 0, 1)
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+ FIELD(IRS_SAVE_VM_STATUSR, Q, 1, 1)
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+
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+REG32(IRS_MEC_IDR, 0x340)
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+ FIELD(IRS_MEC_IDR, MECIDSIZE, 0, 4)
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+
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+REG32(IRS_MEC_MECID_R, 0x344)
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+ FIELD(IRS_MEC_MICID_R, MECID, 0, 16)
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+
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+REG32(IRS_MPAM_IDR, 0x380)
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+ FIELD(IRS_MPAM_IDR, PARTID_MAX, 0, 16)
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+ FIELD(IRS_MPAM_IDR, PMG_MAX, 16, 8)
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+ FIELD(IRS_MPAM_IDR, HAS_MPAM_SP, 24, 1)
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+
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+REG32(IRS_MPAM_PARTID_R, 0x384)
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+ FIELD(IRS_MPAM_IDR, PARTID, 0, 16)
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+ FIELD(IRS_MPAM_IDR, PMG, 16, 8)
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+ FIELD(IRS_MPAM_IDR, MPAM_SP, 24, 2)
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+ FIELD(IRS_MPAM_IDR, IDLE, 31, 1)
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+
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+REG64(IRS_SWERR_STATUSR, 0x3c0)
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+ FIELD(IRS_SWERR_STATUSR, V, 0, 1)
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+ FIELD(IRS_SWERR_STATUSR, S0V, 1, 1)
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+ FIELD(IRS_SWERR_STATUSR, S1V, 2, 1)
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+ FIELD(IRS_SWERR_STATUSR, OF, 3, 1)
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+ FIELD(IRS_SWERR_STATUSR, EC, 16, 8)
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+ FIELD(IRS_SWERR_STATUSR, IMP_EC, 24, 8)
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+
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+REG64(IRS_SWERR_SYNDROMER0, 0x3c8)
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+ FIELD(IRS_SWERR_SYNDROMER0, VM_ID, 0, 16)
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+ FIELD(IRS_SWERR_SYNDROMER0, ID, 32, 24)
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+ FIELD(IRS_SWERR_SYNDROMER0, TYPE, 60, 3)
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+ FIELD(IRS_SWERR_SYNDROMER0, VIRTUAL, 63, 1)
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+
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+REG64(IRS_SWERR_SYNDROMER1, 0x3d0)
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+ FIELD(IRS_SWERR_SYNDROMER2, ADDR, 3, 53)
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+
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static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{