@samitouri / QOSamiQemu / commits / 96009c0fb6

target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1

The ICC_APR_EL1 GICv5 cpuif register records the physical active priorities. Since the GICv5 always uses 5 bits of priority, this register always has 32 non-RES0 bits, and we don't need the complicated GICv3 setup where there might be 1, 2 or 4 APR registers. ICC_HAPR_EL1 is a read-only register which reports the current running priority. This is defined to be the lowest set bit (i.e. the highest priority) in the APR, or the Idle priority 0xff if there are no active interrupts, so it is effectively a convenience re-presentation of the APR register data. The APR register is banked per interrupt domain; ICC_APR_EL1 accesses the version of the register corresponding to the current logical interrupt domain. The APR data for the final domain (EL3) is accessed via ICC_APR_EL3. Although we are starting with an EL1-only implementation, we define the CPU state as banked here so we don't have to change our representation of it later when we add EL3 and RME support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-42-peter.maydell@linaro.org

Peter Maydell committed Mar 27, 2026 at 11:16 UTC 96009c0fb6f8099f697b2809bcb5b8adcf180874

3 files changed +64

include/hw/intc/arm_gicv5_types.h

@@ -84,4 +84,6 @@ typedef enum GICv5TriggerMode {

84 GICV5_TRIGGER_LEVEL = 1,

85 } GICv5TriggerMode;

87 +#define PRIO_IDLE 0xff

88 +

89 #endif

target/arm/cpu.h

@@ -34,6 +34,7 @@

34 #include "target/arm/gtimer.h"

35 #include "target/arm/cpu-sysregs.h"

36 #include "target/arm/mmuidx.h"

37 +#include "hw/intc/arm_gicv5_types.h"

39 #define EXCP_UDEF 1 /* undefined instruction */

40 #define EXCP_SWI 2 /* software interrupt */

@@ -602,6 +603,7 @@ typedef struct CPUArchState {

603 struct {

604 /* GICv5 CPU interface data */

605 uint64_t icc_icsr_el1;

606 + uint64_t icc_apr[NUM_GICV5_DOMAINS];

607 /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */

608 uint64_t ppi_active[GICV5_NUM_PPIS / 64];

609 uint64_t ppi_hm[GICV5_NUM_PPIS / 64];

target/arm/tcg/gicv5-cpuif.c

+60

@@ -95,6 +95,16 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)

95 return gicv5_logical_domain(env);

96 }

98 +static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)

99 +{

100 + /*

101 + * Return the current running priority; this is the lowest set bit in

102 + * the Active Priority Register, or the idle priority if none (D_XMBQZ)

103 + */

104 + uint64_t hap = ctz64(env->gicv5_cpuif.icc_apr[domain]);

105 + return hap < 32 ? hap : PRIO_IDLE;

106 +}

107 +

108 static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,

109 uint64_t value)

110 {

@@ -231,6 +241,44 @@ static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,

241 raw_write(env, ri, value);

242 }

243

244 +/*

245 + * ICC_APR_EL1 is banked and reads/writes as the version for the

246 + * current logical interrupt domain.

247 + */

248 +static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,

249 + uint64_t value)

250 +{

251 + /*

252 + * With an architectural 5 bits of priority, this register has 32

253 + * non-RES0 bits

254 + */

255 + GICv5Domain domain = gicv5_logical_domain(env);

256 + value &= 0xffffffff;

257 + env->gicv5_cpuif.icc_apr[domain] = value;

258 +}

259 +

260 +static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)

261 +{

262 + GICv5Domain domain = gicv5_logical_domain(env);

263 + return env->gicv5_cpuif.icc_apr[domain];

264 +}

265 +

266 +static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)

267 +{

268 + for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_apr); i++) {

269 + env->gicv5_cpuif.icc_apr[i] = 0;

270 + }

271 +}

272 +

273 +static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)

274 +{

275 + /*

276 + * ICC_HAPR_EL1 reports the current running priority, which can be

277 + * calculated from the APR register.

278 + */

279 + return gic_running_prio(env, gicv5_current_phys_domain(env));

280 +}

281 +

282 static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {

283 /*

284 * Barrier: wait until the effects of a cpuif system register

@@ -382,6 +430,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {

430 .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]),

431 .writefn = gic_ppi_spend_write,

432 },

433 + { .name = "ICC_APR_EL1", .state = ARM_CP_STATE_AA64,

434 + .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 0,

435 + .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,

436 + .readfn = gic_icc_apr_el1_read,

437 + .writefn = gic_icc_apr_el1_write,

438 + .resetfn = gic_icc_apr_el1_reset,

439 + },

440 + { .name = "ICC_HAPR_EL1", .state = ARM_CP_STATE_AA64,

441 + .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,

442 + .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,

443 + .readfn = gic_icc_hapr_el1_read, .raw_writefn = arm_cp_write_ignore,

444 + },

445 };

446

447 void define_gicv5_cpuif_regs(ARMCPU *cpu)