target/arm: Allow 'aarch64=off' to be set for TCG CPUs
Allow the 'aarch64=off' property, which is currently KVM-only, to be set for TCG CPUs also. Note that we don't permit it on the qemu-aarch64 user-mode binary: this makes no sense as that executable can only handle AArch64 syscalls (and it would also assert at startup since it doesn't compile in the A32-specific GDB xml files like arm-neon.xml). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260416165353.589569-3-peter.maydell@linaro.org
Peter Maydell committed
Apr 16, 2026 at 17:53 UTC
970ea8478c059a7b753b21b60b4d7aa10944f120
4 files changed
+45
-14
docs/system/arm/cpu-features.rst
+6
-4
@@ -23,10 +23,12 @@ not implement ARMv8-A, will not have the ``aarch64`` CPU property.
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QEMU's support may be limited for some CPU features, only partially
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supporting the feature or only supporting the feature under certain
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configurations. For example, the ``aarch64`` CPU feature, which, when
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-disabled, enables the optional AArch32 CPU feature, is only supported
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-when using the KVM accelerator and when running on a host CPU type that
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-supports the feature. While ``aarch64`` currently only works with KVM,
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-it could work with TCG. CPU features that are specific to KVM are
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+disabled, enables the optional AArch32 CPU feature, can only be set to
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+``off`` on the TCG and KVM accelerators, and it cannot be set to
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+``off`` under KVM unless running on a host CPU type that supports
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+running guests in AArch32.
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+
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+CPU features that are inherently specific to KVM are
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prefixed with "kvm-" and are described in "KVM VCPU Features".
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CPU Feature Probing
target/arm/cpu-features.h
+5
@@ -1071,6 +1071,11 @@ static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
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return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;
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}
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+static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id)
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+{
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+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >= 2;
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+}
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+
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static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
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{
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return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;
target/arm/cpu.c
+32
-4
@@ -1244,10 +1244,38 @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
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* uniform execution state like do_interrupt.
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*/
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if (value == false) {
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- if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
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- error_setg(errp, "'aarch64' feature cannot be disabled "
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- "unless KVM is enabled and 32-bit EL1 "
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- "is supported");
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+ if (kvm_enabled()) {
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+ if (!kvm_arm_aarch32_supported()) {
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+ error_setg(errp, "'aarch64' feature cannot be disabled for KVM "
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+ "because this host does not support 32-bit EL1");
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+ return;
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+ }
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+ } else if (tcg_enabled()) {
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+#ifdef CONFIG_USER_ONLY
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+ error_setg(errp, "'aarch64' feature cannot be disabled for "
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+ "usermode emulator qemu-aarch64; use qemu-arm instead");
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+ return;
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+#else
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+ bool aa32_at_highest_el;
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+ if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
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+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el3, cpu);
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+ } else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
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+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el2, cpu);
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+ } else {
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+ aa32_at_highest_el = cpu_isar_feature(aa64_aa32_el1, cpu);
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+ }
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+
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+ if (!aa32_at_highest_el) {
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+ error_setg(errp, "'aarch64' feature cannot be disabled for "
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+ "this TCG CPU because it does not support 32-bit "
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+ "execution at its highest implemented exception "
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+ "level");
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+ return;
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+ }
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+#endif
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+ } else {
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+ error_setg(errp, "'aarch64' feature cannot be disabled for "
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+ "this accelerator");
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return;
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}
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unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
tests/qtest/arm-cpu-features.c
+2
-6
@@ -493,12 +493,8 @@ static void test_query_cpu_model_expansion(const void *data)
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sve_tests_default(qts, "max");
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pauth_tests_default(qts, "max");
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- /* Test that features that depend on KVM generate errors without. */
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- assert_error(qts, "max",
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- "'aarch64' feature cannot be disabled "
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- "unless KVM is enabled and 32-bit EL1 "
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- "is supported",
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- "{ 'aarch64': false }");
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+ /* TCG allows us to turn off AArch64 on the 'max' CPU type */
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+ assert_set_feature(qts, "max", "aarch64", false);
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}
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qtest_quit(qts);