hw/intc: riscv_aplic: Add reset API to APLIC
Clearing APLIC registers and qemu_irq in the reset function Signed-off-by: Jim Shu <jim.shu@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Message-ID: <20260428160103.3551125-3-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Jim Shu committed
Apr 29, 2026 at 00:01 UTC
99bfcd329aa2441f3a08554659d2c3ee6453f9df
1 file changed
+40
-5
hw/intc/riscv_aplic.c
+40
-5
@@ -892,6 +892,44 @@ static const MemoryRegionOps riscv_aplic_ops = {
892
}
893
};
894
895
+static void riscv_aplic_reset_enter(Object *obj, ResetType type)
896
+{
897
+ RISCVAPLICState *aplic = RISCV_APLIC(obj);
898
+ int i;
899
+
900
+ aplic->domaincfg = 0;
901
+ memset(aplic->sourcecfg, 0, sizeof(uint32_t) * aplic->num_irqs);
902
+ memset(aplic->target, 0, sizeof(uint32_t) * aplic->num_irqs);
903
+ if (!aplic->msimode) {
904
+ for (i = 0; i < aplic->num_irqs; i++) {
905
+ aplic->target[i] = 1;
906
+ }
907
+ }
908
+
909
+ for (i = 0; i < aplic->num_irqs ; i++) {
910
+ riscv_aplic_set_enabled_raw(aplic, i, false);
911
+ }
912
+
913
+ /* Need to unlock [ms]msicfgaddrh.L */
914
+ aplic->mmsicfgaddr = 0;
915
+ aplic->mmsicfgaddrH = 0;
916
+ aplic->smsicfgaddr = 0;
917
+ aplic->smsicfgaddrH = 0;
918
+
919
+ if (!aplic->msimode) {
920
+ /* Reset IDC registers only in non-MSI mode */
921
+ for (i = 0; i < aplic->num_harts; i++) {
922
+ aplic->idelivery[i] = 0;
923
+ aplic->iforce[i] = 0;
924
+ aplic->ithreshold[i] = 0;
925
+ }
926
+
927
+ for (i = 0; i < aplic->num_harts; i++) {
928
+ qemu_irq_lower(aplic->external_irqs[i]);
929
+ }
930
+ }
931
+}
932
+
933
static void riscv_aplic_realize(DeviceState *dev, Error **errp)
934
{
935
uint32_t i;
@@ -925,11 +963,6 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
963
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
964
aplic->state = g_new0(uint32_t, aplic->num_irqs);
965
aplic->target = g_new0(uint32_t, aplic->num_irqs);
928
- if (!aplic->msimode) {
929
- for (i = 0; i < aplic->num_irqs; i++) {
930
- aplic->target[i] = 1;
931
- }
932
- }
966
aplic->idelivery = g_new0(uint32_t, aplic->num_harts);
967
aplic->iforce = g_new0(uint32_t, aplic->num_harts);
968
aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
@@ -1014,9 +1047,11 @@ static const VMStateDescription vmstate_riscv_aplic = {
1047
static void riscv_aplic_class_init(ObjectClass *klass, const void *data)
1048
{
1049
DeviceClass *dc = DEVICE_CLASS(klass);
1050
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
1051
1052
device_class_set_props(dc, riscv_aplic_properties);
1053
dc->realize = riscv_aplic_realize;
1054
+ rc->phases.enter = riscv_aplic_reset_enter;
1055
dc->vmsd = &vmstate_riscv_aplic;
1056
}
1057