tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names
Mechanical replacement of instruction format names of the form 'I3206' etc with more useful names. Where possible, names from a64.decode are used. Includes manual fixes to whitespace. Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20260402-aarch64-tcg-instruction-format-rename2-v1-1-0998a08a515c@linaro.org>
Jim MacArthur committed
Apr 2, 2026 at 15:20 UTC
9a9209c64a53af786d007930f7b84705c048bc14
1 file changed
+490
-472
tcg/aarch64/tcg-target.c.inc
+490
-472
@@ -399,256 +399,256 @@ typedef enum {
399
instruction group is described. */
400
typedef enum {
401
/* Compare and branch (immediate). */
402
- I3201_CBZ = 0x34000000,
403
- I3201_CBNZ = 0x35000000,
402
+ Icbz_CBZ = 0x34000000,
403
+ Icbz_CBNZ = 0x35000000,
404
405
/* Conditional branch (immediate). */
406
- I3202_B_C = 0x54000000,
406
+ Ibcond_imm_B_C = 0x54000000,
407
408
/* Test and branch (immediate). */
409
- I3205_TBZ = 0x36000000,
410
- I3205_TBNZ = 0x37000000,
409
+ Itbz_TBZ = 0x36000000,
410
+ Itbz_TBNZ = 0x37000000,
411
412
/* Unconditional branch (immediate). */
413
- I3206_B = 0x14000000,
414
- I3206_BL = 0x94000000,
413
+ Ibranch_B = 0x14000000,
414
+ Ibranch_BL = 0x94000000,
415
416
/* Unconditional branch (register). */
417
- I3207_BR = 0xd61f0000,
418
- I3207_BLR = 0xd63f0000,
419
- I3207_RET = 0xd65f0000,
417
+ Ibcond_reg_BR = 0xd61f0000,
418
+ Ibcond_reg_BLR = 0xd63f0000,
419
+ Ibcond_reg_RET = 0xd65f0000,
420
421
/* AdvSIMD load/store single structure. */
422
- I3303_LD1R = 0x0d40c000,
422
+ Isimd_loadrep_LD1R = 0x0d40c000,
423
424
/* Load literal for loading the address at pc-relative offset */
425
- I3305_LDR = 0x58000000,
426
- I3305_LDR_v64 = 0x5c000000,
427
- I3305_LDR_v128 = 0x9c000000,
425
+ Ildlit_LDR = 0x58000000,
426
+ Ildlit_LDR_v64 = 0x5c000000,
427
+ Ildlit_LDR_v128 = 0x9c000000,
428
429
/* Load/store exclusive. */
430
- I3306_LDXP = 0xc8600000,
431
- I3306_STXP = 0xc8200000,
430
+ Istxp_LDXP = 0xc8600000,
431
+ Istxp_STXP = 0xc8200000,
432
433
/* Load/store register. Described here as 3.3.12, but the helper
434
that emits them can transform to 3.3.10 or 3.3.13. */
435
- I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
436
- I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,
437
- I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,
438
- I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,
435
+ Ildst_imm_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
436
+ Ildst_imm_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,
437
+ Ildst_imm_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,
438
+ Ildst_imm_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,
439
440
- I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,
441
- I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,
442
- I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,
443
- I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,
440
+ Ildst_imm_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,
441
+ Ildst_imm_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,
442
+ Ildst_imm_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,
443
+ Ildst_imm_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,
444
445
- I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,
446
- I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,
445
+ Ildst_imm_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,
446
+ Ildst_imm_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,
447
448
- I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,
449
- I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
450
- I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
448
+ Ildst_imm_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,
449
+ Ildst_imm_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
450
+ Ildst_imm_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
451
452
- I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
453
- I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
452
+ Ildst_imm_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
453
+ Ildst_imm_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
454
455
- I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
456
- I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
455
+ Ildst_imm_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
456
+ Ildst_imm_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
457
458
- I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
459
- I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
458
+ Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
459
+ Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
460
461
- I3312_TO_I3310 = 0x00200800,
462
- I3312_TO_I3313 = 0x01000000,
461
+ Ildst_imm_TO_I3310 = 0x00200800,
462
+ Ildst_imm_TO_I3313 = 0x01000000,
463
464
/* Load/store register pair instructions. */
465
- I3314_LDP = 0x28400000,
466
- I3314_STP = 0x28000000,
465
+ Ildstpair_LDP = 0x28400000,
466
+ Ildstpair_STP = 0x28000000,
467
468
/* Add/subtract immediate instructions. */
469
- I3401_ADDI = 0x11000000,
470
- I3401_ADDSI = 0x31000000,
471
- I3401_SUBI = 0x51000000,
472
- I3401_SUBSI = 0x71000000,
469
+ Iaddsub_imm_ADDI = 0x11000000,
470
+ Iaddsub_imm_ADDSI = 0x31000000,
471
+ Iaddsub_imm_SUBI = 0x51000000,
472
+ Iaddsub_imm_SUBSI = 0x71000000,
473
474
/* Bitfield instructions. */
475
- I3402_BFM = 0x33000000,
476
- I3402_SBFM = 0x13000000,
477
- I3402_UBFM = 0x53000000,
475
+ Ibitfield_BFM = 0x33000000,
476
+ Ibitfield_SBFM = 0x13000000,
477
+ Ibitfield_UBFM = 0x53000000,
478
479
/* Extract instruction. */
480
- I3403_EXTR = 0x13800000,
480
+ Iextract_EXTR = 0x13800000,
481
482
/* Logical immediate instructions. */
483
- I3404_ANDI = 0x12000000,
484
- I3404_ORRI = 0x32000000,
485
- I3404_EORI = 0x52000000,
486
- I3404_ANDSI = 0x72000000,
483
+ Ilogic_imm_ANDI = 0x12000000,
484
+ Ilogic_imm_ORRI = 0x32000000,
485
+ Ilogic_imm_EORI = 0x52000000,
486
+ Ilogic_imm_ANDSI = 0x72000000,
487
488
/* Move wide immediate instructions. */
489
- I3405_MOVN = 0x12800000,
490
- I3405_MOVZ = 0x52800000,
491
- I3405_MOVK = 0x72800000,
489
+ Imovw_MOVN = 0x12800000,
490
+ Imovw_MOVZ = 0x52800000,
491
+ Imovw_MOVK = 0x72800000,
492
493
/* PC relative addressing instructions. */
494
- I3406_ADR = 0x10000000,
495
- I3406_ADRP = 0x90000000,
494
+ Ipcrel_ADR = 0x10000000,
495
+ Ipcrel_ADRP = 0x90000000,
496
497
/* Add/subtract extended register instructions. */
498
- I3501_ADD = 0x0b200000,
498
+ Iaddsub_ext_ADD = 0x0b200000,
499
500
/* Add/subtract shifted register instructions (without a shift). */
501
- I3502_ADD = 0x0b000000,
502
- I3502_ADDS = 0x2b000000,
503
- I3502_SUB = 0x4b000000,
504
- I3502_SUBS = 0x6b000000,
501
+ Iaddsub_shift_ADD = 0x0b000000,
502
+ Iaddsub_shift_ADDS = 0x2b000000,
503
+ Iaddsub_shift_SUB = 0x4b000000,
504
+ Iaddsub_shift_SUBS = 0x6b000000,
505
506
/* Add/subtract shifted register instructions (with a shift). */
507
- I3502S_ADD_LSL = I3502_ADD,
507
+ Iaddsub_realshift_ADD_LSL = Iaddsub_shift_ADD,
508
509
/* Add/subtract with carry instructions. */
510
- I3503_ADC = 0x1a000000,
511
- I3503_ADCS = 0x3a000000,
512
- I3503_SBC = 0x5a000000,
513
- I3503_SBCS = 0x7a000000,
510
+ Irrr_sf_ADC = 0x1a000000,
511
+ Irrr_sf_ADCS = 0x3a000000,
512
+ Irrr_sf_SBC = 0x5a000000,
513
+ Irrr_sf_SBCS = 0x7a000000,
514
515
/* Conditional select instructions. */
516
- I3506_CSEL = 0x1a800000,
517
- I3506_CSINC = 0x1a800400,
518
- I3506_CSINV = 0x5a800000,
519
- I3506_CSNEG = 0x5a800400,
516
+ Icsel_CSEL = 0x1a800000,
517
+ Icsel_CSINC = 0x1a800400,
518
+ Icsel_CSINV = 0x5a800000,
519
+ Icsel_CSNEG = 0x5a800400,
520
521
/* Data-processing (1 source) instructions. */
522
- I3507_CLZ = 0x5ac01000,
523
- I3507_RBIT = 0x5ac00000,
524
- I3507_REV = 0x5ac00000, /* + size << 10 */
522
+ Irr_sf_CLZ = 0x5ac01000,
523
+ Irr_sf_RBIT = 0x5ac00000,
524
+ Irr_sf_REV = 0x5ac00000, /* + size << 10 */
525
526
/* Data-processing (2 source) instructions. */
527
- I3508_LSLV = 0x1ac02000,
528
- I3508_LSRV = 0x1ac02400,
529
- I3508_ASRV = 0x1ac02800,
530
- I3508_RORV = 0x1ac02c00,
531
- I3508_SMULH = 0x9b407c00,
532
- I3508_UMULH = 0x9bc07c00,
533
- I3508_UDIV = 0x1ac00800,
534
- I3508_SDIV = 0x1ac00c00,
527
+ Irrr_LSLV = 0x1ac02000,
528
+ Irrr_LSRV = 0x1ac02400,
529
+ Irrr_ASRV = 0x1ac02800,
530
+ Irrr_RORV = 0x1ac02c00,
531
+ Irrr_SMULH = 0x9b407c00,
532
+ Irrr_UMULH = 0x9bc07c00,
533
+ Irrr_UDIV = 0x1ac00800,
534
+ Irrr_SDIV = 0x1ac00c00,
535
536
/* Data-processing (3 source) instructions. */
537
- I3509_MADD = 0x1b000000,
538
- I3509_MSUB = 0x1b008000,
537
+ Irrrr_MADD = 0x1b000000,
538
+ Irrrr_MSUB = 0x1b008000,
539
540
/* Logical shifted register instructions (without a shift). */
541
- I3510_AND = 0x0a000000,
542
- I3510_BIC = 0x0a200000,
543
- I3510_ORR = 0x2a000000,
544
- I3510_ORN = 0x2a200000,
545
- I3510_EOR = 0x4a000000,
546
- I3510_EON = 0x4a200000,
547
- I3510_ANDS = 0x6a000000,
541
+ Ilogic_shift_AND = 0x0a000000,
542
+ Ilogic_shift_BIC = 0x0a200000,
543
+ Ilogic_shift_ORR = 0x2a000000,
544
+ Ilogic_shift_ORN = 0x2a200000,
545
+ Ilogic_shift_EOR = 0x4a000000,
546
+ Ilogic_shift_EON = 0x4a200000,
547
+ Ilogic_shift_ANDS = 0x6a000000,
548
549
/* Logical shifted register instructions (with a shift). */
550
- I3502S_AND_LSR = I3510_AND | (1 << 22),
550
+ Iaddsub_realshift_AND_LSR = Ilogic_shift_AND | (1 << 22),
551
552
/* AdvSIMD copy */
553
- I3605_DUP = 0x0e000400,
554
- I3605_INS = 0x4e001c00,
555
- I3605_UMOV = 0x0e003c00,
553
+ Isimd_copy_DUP = 0x0e000400,
554
+ Isimd_copy_INS = 0x4e001c00,
555
+ Isimd_copy_UMOV = 0x0e003c00,
556
557
/* AdvSIMD modified immediate */
558
- I3606_MOVI = 0x0f000400,
559
- I3606_MVNI = 0x2f000400,
560
- I3606_BIC = 0x2f001400,
561
- I3606_ORR = 0x0f001400,
558
+ Isimd_imm_MOVI = 0x0f000400,
559
+ Isimd_imm_MVNI = 0x2f000400,
560
+ Isimd_imm_BIC = 0x2f001400,
561
+ Isimd_imm_ORR = 0x0f001400,
562
563
/* AdvSIMD scalar shift by immediate */
564
- I3609_SSHR = 0x5f000400,
565
- I3609_SSRA = 0x5f001400,
566
- I3609_SHL = 0x5f005400,
567
- I3609_USHR = 0x7f000400,
568
- I3609_USRA = 0x7f001400,
569
- I3609_SLI = 0x7f005400,
564
+ Iq_shift_SSHR = 0x5f000400,
565
+ Iq_shift_SSRA = 0x5f001400,
566
+ Iq_shift_SHL = 0x5f005400,
567
+ Iq_shift_USHR = 0x7f000400,
568
+ Iq_shift_USRA = 0x7f001400,
569
+ Iq_shift_SLI = 0x7f005400,
570
571
/* AdvSIMD scalar three same */
572
- I3611_SQADD = 0x5e200c00,
573
- I3611_SQSUB = 0x5e202c00,
574
- I3611_CMGT = 0x5e203400,
575
- I3611_CMGE = 0x5e203c00,
576
- I3611_SSHL = 0x5e204400,
577
- I3611_ADD = 0x5e208400,
578
- I3611_CMTST = 0x5e208c00,
579
- I3611_UQADD = 0x7e200c00,
580
- I3611_UQSUB = 0x7e202c00,
581
- I3611_CMHI = 0x7e203400,
582
- I3611_CMHS = 0x7e203c00,
583
- I3611_USHL = 0x7e204400,
584
- I3611_SUB = 0x7e208400,
585
- I3611_CMEQ = 0x7e208c00,
572
+ Irrr_e_SQADD = 0x5e200c00,
573
+ Irrr_e_SQSUB = 0x5e202c00,
574
+ Irrr_e_CMGT = 0x5e203400,
575
+ Irrr_e_CMGE = 0x5e203c00,
576
+ Irrr_e_SSHL = 0x5e204400,
577
+ Irrr_e_ADD = 0x5e208400,
578
+ Irrr_e_CMTST = 0x5e208c00,
579
+ Irrr_e_UQADD = 0x7e200c00,
580
+ Irrr_e_UQSUB = 0x7e202c00,
581
+ Irrr_e_CMHI = 0x7e203400,
582
+ Irrr_e_CMHS = 0x7e203c00,
583
+ Irrr_e_USHL = 0x7e204400,
584
+ Irrr_e_SUB = 0x7e208400,
585
+ Irrr_e_CMEQ = 0x7e208c00,
586
587
/* AdvSIMD scalar two-reg misc */
588
- I3612_CMGT0 = 0x5e208800,
589
- I3612_CMEQ0 = 0x5e209800,
590
- I3612_CMLT0 = 0x5e20a800,
591
- I3612_ABS = 0x5e20b800,
592
- I3612_CMGE0 = 0x7e208800,
593
- I3612_CMLE0 = 0x7e209800,
594
- I3612_NEG = 0x7e20b800,
588
+ Isimd_rr_CMGT0 = 0x5e208800,
589
+ Isimd_rr_CMEQ0 = 0x5e209800,
590
+ Isimd_rr_CMLT0 = 0x5e20a800,
591
+ Isimd_rr_ABS = 0x5e20b800,
592
+ Isimd_rr_CMGE0 = 0x7e208800,
593
+ Isimd_rr_CMLE0 = 0x7e209800,
594
+ Isimd_rr_NEG = 0x7e20b800,
595
596
/* AdvSIMD shift by immediate */
597
- I3614_SSHR = 0x0f000400,
598
- I3614_SSRA = 0x0f001400,
599
- I3614_SHL = 0x0f005400,
600
- I3614_SLI = 0x2f005400,
601
- I3614_USHR = 0x2f000400,
602
- I3614_USRA = 0x2f001400,
597
+ Isimd_shift_imm_SSHR = 0x0f000400,
598
+ Isimd_shift_imm_SSRA = 0x0f001400,
599
+ Isimd_shift_imm_SHL = 0x0f005400,
600
+ Isimd_shift_imm_SLI = 0x2f005400,
601
+ Isimd_shift_imm_USHR = 0x2f000400,
602
+ Isimd_shift_imm_USRA = 0x2f001400,
603
604
/* AdvSIMD three same. */
605
- I3616_ADD = 0x0e208400,
606
- I3616_AND = 0x0e201c00,
607
- I3616_BIC = 0x0e601c00,
608
- I3616_BIF = 0x2ee01c00,
609
- I3616_BIT = 0x2ea01c00,
610
- I3616_BSL = 0x2e601c00,
611
- I3616_EOR = 0x2e201c00,
612
- I3616_MUL = 0x0e209c00,
613
- I3616_ORR = 0x0ea01c00,
614
- I3616_ORN = 0x0ee01c00,
615
- I3616_SUB = 0x2e208400,
616
- I3616_CMGT = 0x0e203400,
617
- I3616_CMGE = 0x0e203c00,
618
- I3616_CMTST = 0x0e208c00,
619
- I3616_CMHI = 0x2e203400,
620
- I3616_CMHS = 0x2e203c00,
621
- I3616_CMEQ = 0x2e208c00,
622
- I3616_SMAX = 0x0e206400,
623
- I3616_SMIN = 0x0e206c00,
624
- I3616_SSHL = 0x0e204400,
625
- I3616_SQADD = 0x0e200c00,
626
- I3616_SQSUB = 0x0e202c00,
627
- I3616_UMAX = 0x2e206400,
628
- I3616_UMIN = 0x2e206c00,
629
- I3616_UQADD = 0x2e200c00,
630
- I3616_UQSUB = 0x2e202c00,
631
- I3616_USHL = 0x2e204400,
605
+ Iqrrr_e_ADD = 0x0e208400,
606
+ Iqrrr_e_AND = 0x0e201c00,
607
+ Iqrrr_e_BIC = 0x0e601c00,
608
+ Iqrrr_e_BIF = 0x2ee01c00,
609
+ Iqrrr_e_BIT = 0x2ea01c00,
610
+ Iqrrr_e_BSL = 0x2e601c00,
611
+ Iqrrr_e_EOR = 0x2e201c00,
612
+ Iqrrr_e_MUL = 0x0e209c00,
613
+ Iqrrr_e_ORR = 0x0ea01c00,
614
+ Iqrrr_e_ORN = 0x0ee01c00,
615
+ Iqrrr_e_SUB = 0x2e208400,
616
+ Iqrrr_e_CMGT = 0x0e203400,
617
+ Iqrrr_e_CMGE = 0x0e203c00,
618
+ Iqrrr_e_CMTST = 0x0e208c00,
619
+ Iqrrr_e_CMHI = 0x2e203400,
620
+ Iqrrr_e_CMHS = 0x2e203c00,
621
+ Iqrrr_e_CMEQ = 0x2e208c00,
622
+ Iqrrr_e_SMAX = 0x0e206400,
623
+ Iqrrr_e_SMIN = 0x0e206c00,
624
+ Iqrrr_e_SSHL = 0x0e204400,
625
+ Iqrrr_e_SQADD = 0x0e200c00,
626
+ Iqrrr_e_SQSUB = 0x0e202c00,
627
+ Iqrrr_e_UMAX = 0x2e206400,
628
+ Iqrrr_e_UMIN = 0x2e206c00,
629
+ Iqrrr_e_UQADD = 0x2e200c00,
630
+ Iqrrr_e_UQSUB = 0x2e202c00,
631
+ Iqrrr_e_USHL = 0x2e204400,
632
633
/* AdvSIMD two-reg misc. */
634
- I3617_CMGT0 = 0x0e208800,
635
- I3617_CMEQ0 = 0x0e209800,
636
- I3617_CMLT0 = 0x0e20a800,
637
- I3617_CMGE0 = 0x2e208800,
638
- I3617_CMLE0 = 0x2e209800,
639
- I3617_NOT = 0x2e205800,
640
- I3617_ABS = 0x0e20b800,
641
- I3617_NEG = 0x2e20b800,
634
+ Iqrr_e_CMGT0 = 0x0e208800,
635
+ Iqrr_e_CMEQ0 = 0x0e209800,
636
+ Iqrr_e_CMLT0 = 0x0e20a800,
637
+ Iqrr_e_CMGE0 = 0x2e208800,
638
+ Iqrr_e_CMLE0 = 0x2e209800,
639
+ Iqrr_e_NOT = 0x2e205800,
640
+ Iqrr_e_ABS = 0x0e20b800,
641
+ Iqrr_e_NEG = 0x2e20b800,
642
643
/* System instructions. */
644
- NOP = 0xd503201f,
645
- DMB_ISH = 0xd50338bf,
646
- DMB_LD = 0x00000100,
647
- DMB_ST = 0x00000200,
648
-
649
- BTI_C = 0xd503245f,
650
- BTI_J = 0xd503249f,
651
- BTI_JC = 0xd50324df,
644
+ NOP = 0xd503201f,
645
+ DMB_ISH = 0xd50338bf,
646
+ DMB_LD = 0x00000100,
647
+ DMB_ST = 0x00000200,
648
+
649
+ BTI_C = 0xd503245f,
650
+ BTI_J = 0xd503249f,
651
+ BTI_JC = 0xd50324df,
652
} AArch64Insn;
653
654
static inline uint32_t tcg_in32(TCGContext *s)
@@ -661,37 +661,37 @@ static inline uint32_t tcg_in32(TCGContext *s)
661
#define tcg_out_insn(S, FMT, OP, ...) \
662
glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
663
664
-static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
664
+static void tcg_out_insn_simd_loadrep(TCGContext *s, AArch64Insn insn, bool q,
665
TCGReg rt, TCGReg rn, unsigned size)
666
{
667
tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
668
}
669
670
-static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
670
+static void tcg_out_insn_ldlit(TCGContext *s, AArch64Insn insn,
671
int imm19, TCGReg rt)
672
{
673
tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
674
}
675
676
-static void tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, TCGReg rs,
676
+static void tcg_out_insn_stxp(TCGContext *s, AArch64Insn insn, TCGReg rs,
677
TCGReg rt, TCGReg rt2, TCGReg rn)
678
{
679
tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt);
680
}
681
682
-static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
682
+static void tcg_out_insn_cbz(TCGContext *s, AArch64Insn insn, TCGType ext,
683
TCGReg rt, int imm19)
684
{
685
tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);
686
}
687
688
-static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,
688
+static void tcg_out_insn_bcond_imm(TCGContext *s, AArch64Insn insn,
689
TCGCond c, int imm19)
690
{
691
tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);
692
}
693
694
-static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn,
694
+static void tcg_out_insn_tbz(TCGContext *s, AArch64Insn insn,
695
TCGReg rt, int imm6, int imm14)
696
{
697
insn |= (imm6 & 0x20) << (31 - 5);
@@ -699,17 +699,17 @@ static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn,
699
tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt);
700
}
701
702
-static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26)
702
+static void tcg_out_insn_branch(TCGContext *s, AArch64Insn insn, int imm26)
703
{
704
tcg_out32(s, insn | (imm26 & 0x03ffffff));
705
}
706
707
-static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn)
707
+static void tcg_out_insn_bcond_reg(TCGContext *s, AArch64Insn insn, TCGReg rn)
708
{
709
tcg_out32(s, insn | rn << 5);
710
}
711
712
-static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,
712
+static void tcg_out_insn_ldstpair(TCGContext *s, AArch64Insn insn,
713
TCGReg r1, TCGReg r2, TCGReg rn,
714
tcg_target_long ofs, bool pre, bool w)
715
{
@@ -723,8 +723,9 @@ static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,
723
tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);
724
}
725
726
-static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
727
- TCGReg rd, TCGReg rn, uint64_t aimm)
726
+static void tcg_out_insn_addsub_imm(TCGContext *s, AArch64Insn insn,
727
+ TCGType ext, TCGReg rd, TCGReg rn,
728
+ uint64_t aimm)
729
{
730
if (aimm > 0xfff) {
731
tcg_debug_assert((aimm & 0xfff) == 0);
@@ -738,16 +739,17 @@ static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
739
/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4
740
(Logical immediate). Both insn groups have N, IMMR and IMMS fields
741
that feed the DecodeBitMasks pseudo function. */
741
-static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
742
- TCGReg rd, TCGReg rn, int n, int immr, int imms)
742
+static void tcg_out_insn_bitfield(TCGContext *s, AArch64Insn insn, TCGType ext,
743
+ TCGReg rd, TCGReg rn, int n, int immr,
744
+ int imms)
745
{
746
tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10
747
| rn << 5 | rd);
748
}
749
748
-#define tcg_out_insn_3404 tcg_out_insn_3402
750
+#define tcg_out_insn_logic_imm tcg_out_insn_bitfield
751
750
-static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
752
+static void tcg_out_insn_extract(TCGContext *s, AArch64Insn insn, TCGType ext,
753
TCGReg rd, TCGReg rn, TCGReg rm, int imms)
754
{
755
tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10
@@ -756,20 +758,20 @@ static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
758
759
/* This function is used for the Move (wide immediate) instruction group.
760
Note that SHIFT is a full shift count, not the 2 bit HW field. */
759
-static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
761
+static void tcg_out_insn_movw(TCGContext *s, AArch64Insn insn, TCGType ext,
762
TCGReg rd, uint16_t half, unsigned shift)
763
{
764
tcg_debug_assert((shift & ~0x30) == 0);
765
tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
766
}
767
766
-static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
768
+static void tcg_out_insn_pcrel(TCGContext *s, AArch64Insn insn,
769
TCGReg rd, int64_t disp)
770
{
771
tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
772
}
773
772
-static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn,
774
+static inline void tcg_out_insn_addsub_ext(TCGContext *s, AArch64Insn insn,
775
TCGType sf, TCGReg rd, TCGReg rn,
776
TCGReg rm, int opt, int imm3)
777
{
@@ -779,9 +781,11 @@ static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn,
781
782
/* This function is for both 3.5.2 (Add/Subtract shifted register), for
783
the rare occasion when we actually want to supply a shift amount. */
782
-static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
783
- TCGType ext, TCGReg rd, TCGReg rn,
784
- TCGReg rm, int imm6)
784
+static inline void tcg_out_insn_addsub_realshift(TCGContext *s,
785
+ AArch64Insn insn,
786
+ TCGType ext, TCGReg rd,
787
+ TCGReg rn, TCGReg rm,
788
+ int imm6)
789
{
790
tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd);
791
}
@@ -790,36 +794,37 @@ static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
794
and 3.5.10 (Logical shifted register), for the vast majorty of cases
795
when we don't want to apply a shift. Thus it can also be used for
796
3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */
793
-static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,
794
- TCGReg rd, TCGReg rn, TCGReg rm)
797
+static void tcg_out_insn_addsub_shift(TCGContext *s, AArch64Insn insn,
798
+ TCGType ext, TCGReg rd, TCGReg rn,
799
+ TCGReg rm)
800
{
801
tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd);
802
}
803
799
-#define tcg_out_insn_3503 tcg_out_insn_3502
800
-#define tcg_out_insn_3508 tcg_out_insn_3502
801
-#define tcg_out_insn_3510 tcg_out_insn_3502
804
+#define tcg_out_insn_rrr_sf tcg_out_insn_addsub_shift
805
+#define tcg_out_insn_rrr tcg_out_insn_addsub_shift
806
+#define tcg_out_insn_logic_shift tcg_out_insn_addsub_shift
807
803
-static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
808
+static void tcg_out_insn_csel(TCGContext *s, AArch64Insn insn, TCGType ext,
809
TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c)
810
{
811
tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd
812
| tcg_cond_to_aarch64[c] << 12);
813
}
814
810
-static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext,
815
+static void tcg_out_insn_rr_sf(TCGContext *s, AArch64Insn insn, TCGType ext,
816
TCGReg rd, TCGReg rn)
817
{
818
tcg_out32(s, insn | ext << 31 | rn << 5 | rd);
819
}
820
816
-static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
821
+static void tcg_out_insn_rrrr(TCGContext *s, AArch64Insn insn, TCGType ext,
822
TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
823
{
824
tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
825
}
826
822
-static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
827
+static void tcg_out_insn_simd_copy(TCGContext *s, AArch64Insn insn, bool q,
828
TCGReg rd, TCGReg rn, int dst_idx, int src_idx)
829
{
830
/* Note that bit 11 set means general register input. Therefore
@@ -828,47 +833,47 @@ static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
833
| (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
834
}
835
831
-static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
836
+static void tcg_out_insn_simd_imm(TCGContext *s, AArch64Insn insn, bool q,
837
TCGReg rd, bool op, int cmode, uint8_t imm8)
838
{
839
tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
840
| (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
841
}
842
838
-static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn,
843
+static void tcg_out_insn_q_shift(TCGContext *s, AArch64Insn insn,
844
TCGReg rd, TCGReg rn, unsigned immhb)
845
{
846
tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));
847
}
848
844
-static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn,
849
+static void tcg_out_insn_rrr_e(TCGContext *s, AArch64Insn insn,
850
unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
851
{
852
tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16
853
| (rn & 0x1f) << 5 | (rd & 0x1f));
854
}
855
851
-static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn,
856
+static void tcg_out_insn_simd_rr(TCGContext *s, AArch64Insn insn,
857
unsigned size, TCGReg rd, TCGReg rn)
858
{
859
tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));
860
}
861
857
-static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
862
+static void tcg_out_insn_simd_shift_imm(TCGContext *s, AArch64Insn insn, bool q,
863
TCGReg rd, TCGReg rn, unsigned immhb)
864
{
865
tcg_out32(s, insn | q << 30 | immhb << 16
866
| (rn & 0x1f) << 5 | (rd & 0x1f));
867
}
868
864
-static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,
869
+static void tcg_out_insn_qrrr_e(TCGContext *s, AArch64Insn insn, bool q,
870
unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
871
{
872
tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
873
| (rn & 0x1f) << 5 | (rd & 0x1f));
874
}
875
871
-static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
876
+static void tcg_out_insn_qrr_e(TCGContext *s, AArch64Insn insn, bool q,
877
unsigned size, TCGReg rd, TCGReg rn)
878
{
879
tcg_out32(s, insn | q << 30 | (size << 22)
@@ -880,11 +885,11 @@ static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
885
TCGReg regoff)
886
{
887
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
883
- tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
888
+ tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 |
889
0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
890
}
891
887
-static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
892
+static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,
893
TCGReg rd, TCGReg rn, intptr_t offset)
894
{
895
tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
@@ -894,7 +899,7 @@ static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
899
TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
900
{
901
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
897
- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10
902
+ tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10
903
| rn << 5 | (rd & 0x1f));
904
}
905
@@ -912,13 +917,13 @@ static void tcg_out_bti(TCGContext *s, AArch64Insn insn)
917
/* Register to register move using ORR (shifted register with no shift). */
918
static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
919
{
915
- tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
920
+ tcg_out_insn(s, logic_shift, ORR, ext, rd, TCG_REG_XZR, rm);
921
}
922
923
/* Register to register move using ADDI (move to/from SP). */
924
static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
925
{
921
- tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
926
+ tcg_out_insn(s, addsub_imm, ADDI, ext, rd, rn, 0);
927
}
928
929
/* This function is used for the Logical (immediate) instruction group.
@@ -949,7 +954,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
954
c &= 31;
955
}
956
952
- tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
957
+ tcg_out_insn_logic_imm(s, insn, ext, rd, rn, ext, r, c);
958
}
959
960
static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
@@ -961,7 +966,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
966
/* Test all bytes equal first. */
967
if (vece == MO_8) {
968
imm8 = (uint8_t)v64;
964
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
969
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, 0xe, imm8);
970
return;
971
}
972
@@ -977,7 +982,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
982
goto fail_bytes;
983
}
984
}
980
- tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);
985
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 1, 0xe, imm8);
986
return;
987
fail_bytes:
988
@@ -990,11 +995,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
995
uint16_t v16 = v64;
996
997
if (is_shimm16(v16, &cmode, &imm8)) {
993
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
998
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);
999
return;
1000
}
1001
if (is_shimm16(~v16, &cmode, &imm8)) {
997
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
1002
+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);
1003
return;
1004
}
1005
@@ -1002,8 +1007,8 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1007
* Otherwise, all remaining constants can be loaded in two insns:
1008
* rd = v16 & 0xff, rd |= v16 & 0xff00.
1009
*/
1005
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);
1006
- tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);
1010
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, 0x8, v16 & 0xff);
1011
+ tcg_out_insn(s, simd_imm, ORR, q, rd, 0, 0xa, v16 >> 8);
1012
return;
1013
} else if (vece == MO_32) {
1014
uint32_t v32 = v64;
@@ -1012,12 +1017,12 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1017
if (is_shimm32(v32, &cmode, &imm8) ||
1018
is_soimm32(v32, &cmode, &imm8) ||
1019
is_fimm32(v32, &cmode, &imm8)) {
1015
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
1020
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);
1021
return;
1022
}
1023
if (is_shimm32(n32, &cmode, &imm8) ||
1024
is_soimm32(n32, &cmode, &imm8)) {
1020
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
1025
+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);
1026
return;
1027
}
1028
@@ -1027,18 +1032,20 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1032
*/
1033
i = is_shimm32_pair(v32, &cmode, &imm8);
1034
if (i) {
1030
- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);
1031
- tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8));
1035
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);
1036
+ tcg_out_insn(s, simd_imm, ORR, q, rd, 0, i,
1037
+ extract32(v32, i * 4, 8));
1038
return;
1039
}
1040
i = is_shimm32_pair(n32, &cmode, &imm8);
1041
if (i) {
1036
- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);
1037
- tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8));
1042
+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);
1043
+ tcg_out_insn(s, simd_imm, BIC, q, rd, 0, i,
1044
+ extract32(n32, i * 4, 8));
1045
return;
1046
}
1047
} else if (is_fimm64(v64, &cmode, &imm8)) {
1041
- tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8);
1048
+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 1, cmode, imm8);
1049
return;
1050
}
1051
@@ -1048,10 +1055,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1055
*/
1056
if (type == TCG_TYPE_V128) {
1057
new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
1051
- tcg_out_insn(s, 3305, LDR_v128, 0, rd);
1058
+ tcg_out_insn(s, ldlit, LDR_v128, 0, rd);
1059
} else {
1060
new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
1054
- tcg_out_insn(s, 3305, LDR_v64, 0, rd);
1061
+ tcg_out_insn(s, ldlit, LDR_v64, 0, rd);
1062
}
1063
}
1064
@@ -1059,7 +1066,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
1066
TCGReg rd, TCGReg rs)
1067
{
1068
int is_q = type - TCG_TYPE_V64;
1062
- tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);
1069
+ tcg_out_insn(s, simd_copy, DUP, is_q, rd, rs, 1 << vece, 0);
1070
return true;
1071
}
1072
@@ -1070,25 +1077,26 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
1077
1078
if (offset < -0xffffff || offset > 0xffffff) {
1079
tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
1073
- tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
1080
+ tcg_out_insn(s, addsub_shift, ADD, 1, temp, temp, base);
1081
base = temp;
1082
} else {
1076
- AArch64Insn add_insn = I3401_ADDI;
1083
+ AArch64Insn add_insn = Iaddsub_imm_ADDI;
1084
1085
if (offset < 0) {
1079
- add_insn = I3401_SUBI;
1086
+ add_insn = Iaddsub_imm_SUBI;
1087
offset = -offset;
1088
}
1089
if (offset & 0xfff000) {
1083
- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
1090
+ tcg_out_insn_addsub_imm(s, add_insn, 1, temp, base,
1091
+ offset & 0xfff000);
1092
base = temp;
1093
}
1094
if (offset & 0xfff) {
1087
- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
1095
+ tcg_out_insn_addsub_imm(s, add_insn, 1, temp, base, offset & 0xfff);
1096
base = temp;
1097
}
1098
}
1091
- tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
1099
+ tcg_out_insn(s, simd_loadrep, LD1R, type == TCG_TYPE_V128, r, base, vece);
1100
return true;
1101
}
1102
@@ -1124,10 +1132,10 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
1132
/* Speed things up by handling the common case of small positive
1133
and negative values specially. */
1134
if ((value & ~0xffffull) == 0) {
1127
- tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0);
1135
+ tcg_out_insn(s, movw, MOVZ, type, rd, value, 0);
1136
return;
1137
} else if ((ivalue & ~0xffffull) == 0) {
1130
- tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0);
1138
+ tcg_out_insn(s, movw, MOVN, type, rd, ivalue, 0);
1139
return;
1140
}
1141
@@ -1135,7 +1143,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
1143
use the sign-extended value. That lets us match rotated values such
1144
as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */
1145
if (is_limm(svalue)) {
1138
- tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue);
1146
+ tcg_out_logicali(s, Ilogic_imm_ORRI, type, rd, TCG_REG_XZR, svalue);
1147
return;
1148
}
1149
@@ -1145,14 +1153,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
1153
intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr);
1154
tcg_target_long disp = value - src_rx;
1155
if (disp == sextract64(disp, 0, 21)) {
1148
- tcg_out_insn(s, 3406, ADR, rd, disp);
1156
+ tcg_out_insn(s, pcrel, ADR, rd, disp);
1157
return;
1158
}
1159
disp = (value >> 12) - (src_rx >> 12);
1160
if (disp == sextract64(disp, 0, 21)) {
1153
- tcg_out_insn(s, 3406, ADRP, rd, disp);
1161
+ tcg_out_insn(s, pcrel, ADRP, rd, disp);
1162
if (value & 0xfff) {
1155
- tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
1163
+ tcg_out_insn(s, addsub_imm, ADDI, type, rd, rd, value & 0xfff);
1164
}
1165
return;
1166
}
@@ -1161,26 +1169,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
1169
/* Would it take fewer insns to begin with MOVN? */
1170
if (ctpop64(value) >= 32) {
1171
t0 = ivalue;
1164
- opc = I3405_MOVN;
1172
+ opc = Imovw_MOVN;
1173
} else {
1174
t0 = value;
1167
- opc = I3405_MOVZ;
1175
+ opc = Imovw_MOVZ;
1176
}
1177
s0 = ctz64(t0) & (63 & -16);
1178
t1 = t0 & ~(0xffffull << s0);
1179
s1 = ctz64(t1) & (63 & -16);
1180
t2 = t1 & ~(0xffffull << s1);
1181
if (t2 == 0) {
1174
- tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0);
1182
+ tcg_out_insn_movw(s, opc, type, rd, t0 >> s0, s0);
1183
if (t1 != 0) {
1176
- tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1);
1184
+ tcg_out_insn(s, movw, MOVK, type, rd, value >> s1, s1);
1185
}
1186
return;
1187
}
1188
1189
/* For more than 2 insns, dump it into the constant pool. */
1190
new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0);
1183
- tcg_out_insn(s, 3305, LDR, 0, rd);
1191
+ tcg_out_insn(s, ldlit, LDR, 0, rd);
1192
}
1193
1194
static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
@@ -1213,7 +1221,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
1221
1222
/* Small signed offsets can use the unscaled encoding. */
1223
if (offset >= -256 && offset < 256) {
1216
- tcg_out_insn_3312(s, insn, rd, rn, offset);
1224
+ tcg_out_insn_ldst_imm(s, insn, rd, rn, offset);
1225
return;
1226
}
1227
@@ -1234,21 +1242,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
1242
tcg_out_movr(s, type, ret, arg);
1243
break;
1244
} else if (ret < 32) {
1237
- tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
1245
+ tcg_out_insn(s, simd_copy, UMOV, type, ret, arg, 0, 0);
1246
break;
1247
} else if (arg < 32) {
1240
- tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
1248
+ tcg_out_insn(s, simd_copy, INS, 0, ret, arg, 4 << type, 0);
1249
break;
1250
}
1251
/* FALLTHRU */
1252
1253
case TCG_TYPE_V64:
1254
tcg_debug_assert(ret >= 32 && arg >= 32);
1247
- tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
1255
+ tcg_out_insn(s, qrrr_e, ORR, 0, 0, ret, arg, arg);
1256
break;
1257
case TCG_TYPE_V128:
1258
tcg_debug_assert(ret >= 32 && arg >= 32);
1251
- tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
1259
+ tcg_out_insn(s, qrrr_e, ORR, 1, 0, ret, arg, arg);
1260
break;
1261
1262
default:
@@ -1265,19 +1273,19 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1273
1274
switch (type) {
1275
case TCG_TYPE_I32:
1268
- insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);
1276
+ insn = (ret < 32 ? Ildst_imm_LDRW : Ildst_imm_LDRVS);
1277
lgsz = 2;
1278
break;
1279
case TCG_TYPE_I64:
1272
- insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);
1280
+ insn = (ret < 32 ? Ildst_imm_LDRX : Ildst_imm_LDRVD);
1281
lgsz = 3;
1282
break;
1283
case TCG_TYPE_V64:
1276
- insn = I3312_LDRVD;
1284
+ insn = Ildst_imm_LDRVD;
1285
lgsz = 3;
1286
break;
1287
case TCG_TYPE_V128:
1280
- insn = I3312_LDRVQ;
1288
+ insn = Ildst_imm_LDRVQ;
1289
lgsz = 4;
1290
break;
1291
default:
@@ -1294,19 +1302,19 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
1302
1303
switch (type) {
1304
case TCG_TYPE_I32:
1297
- insn = (src < 32 ? I3312_STRW : I3312_STRVS);
1305
+ insn = (src < 32 ? Ildst_imm_STRW : Ildst_imm_STRVS);
1306
lgsz = 2;
1307
break;
1308
case TCG_TYPE_I64:
1301
- insn = (src < 32 ? I3312_STRX : I3312_STRVD);
1309
+ insn = (src < 32 ? Ildst_imm_STRX : Ildst_imm_STRVD);
1310
lgsz = 3;
1311
break;
1312
case TCG_TYPE_V64:
1305
- insn = I3312_STRVD;
1313
+ insn = Ildst_imm_STRVD;
1314
lgsz = 3;
1315
break;
1316
case TCG_TYPE_V128:
1309
- insn = I3312_STRVQ;
1317
+ insn = Ildst_imm_STRVQ;
1318
lgsz = 4;
1319
break;
1320
default:
@@ -1328,34 +1336,34 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
1336
static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
1337
TCGReg rn, unsigned int a, unsigned int b)
1338
{
1331
- tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b);
1339
+ tcg_out_insn(s, bitfield, BFM, ext, rd, rn, ext, a, b);
1340
}
1341
1342
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
1343
TCGReg rn, unsigned int a, unsigned int b)
1344
{
1337
- tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b);
1345
+ tcg_out_insn(s, bitfield, UBFM, ext, rd, rn, ext, a, b);
1346
}
1347
1348
static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
1349
TCGReg rn, unsigned int a, unsigned int b)
1350
{
1343
- tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b);
1351
+ tcg_out_insn(s, bitfield, SBFM, ext, rd, rn, ext, a, b);
1352
}
1353
1354
static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
1355
TCGReg rn, TCGReg rm, unsigned int a)
1356
{
1349
- tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
1357
+ tcg_out_insn(s, extract, EXTR, ext, rd, rn, rm, a);
1358
}
1359
1360
static void tgen_cmp(TCGContext *s, TCGType ext, TCGCond cond,
1361
TCGReg a, TCGReg b)
1362
{
1363
if (is_tst_cond(cond)) {
1356
- tcg_out_insn(s, 3510, ANDS, ext, TCG_REG_XZR, a, b);
1364
+ tcg_out_insn(s, logic_shift, ANDS, ext, TCG_REG_XZR, a, b);
1365
} else {
1358
- tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b);
1366
+ tcg_out_insn(s, addsub_shift, SUBS, ext, TCG_REG_XZR, a, b);
1367
}
1368
}
1369
@@ -1363,13 +1371,13 @@ static void tgen_cmpi(TCGContext *s, TCGType ext, TCGCond cond,
1371
TCGReg a, tcg_target_long b)
1372
{
1373
if (is_tst_cond(cond)) {
1366
- tcg_out_logicali(s, I3404_ANDSI, ext, TCG_REG_XZR, a, b);
1374
+ tcg_out_logicali(s, Ilogic_imm_ANDSI, ext, TCG_REG_XZR, a, b);
1375
} else if (b >= 0) {
1376
tcg_debug_assert(is_aimm(b));
1369
- tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b);
1377
+ tcg_out_insn(s, addsub_imm, SUBSI, ext, TCG_REG_XZR, a, b);
1378
} else {
1379
tcg_debug_assert(is_aimm(-b));
1372
- tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b);
1380
+ tcg_out_insn(s, addsub_imm, ADDSI, ext, TCG_REG_XZR, a, -b);
1381
}
1382
}
1383
@@ -1387,17 +1395,17 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
1395
{
1396
ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;
1397
tcg_debug_assert(offset == sextract64(offset, 0, 26));
1390
- tcg_out_insn(s, 3206, B, offset);
1398
+ tcg_out_insn(s, branch, B, offset);
1399
}
1400
1401
static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *target)
1402
{
1403
ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;
1404
if (offset == sextract64(offset, 0, 26)) {
1397
- tcg_out_insn(s, 3206, BL, offset);
1405
+ tcg_out_insn(s, branch, BL, offset);
1406
} else {
1407
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);
1400
- tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0);
1408
+ tcg_out_insn(s, bcond_reg, BLR, TCG_REG_TMP0);
1409
}
1410
}
1411
@@ -1411,7 +1419,7 @@ static void tcg_out_br(TCGContext *s, TCGLabel *l)
1419
{
1420
if (!l->has_value) {
1421
tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0);
1414
- tcg_out_insn(s, 3206, B, 0);
1422
+ tcg_out_insn(s, branch, B, 0);
1423
} else {
1424
tcg_out_goto(s, l->u.value_ptr);
1425
}
@@ -1422,7 +1430,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
1430
{
1431
tgen_cmp(s, type, c, a, b);
1432
tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
1425
- tcg_out_insn(s, 3202, B_C, c, 0);
1433
+ tcg_out_insn(s, bcond_imm, B_C, c, 0);
1434
}
1435
1436
static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,
@@ -1470,7 +1478,7 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,
1478
if (need_cmp) {
1479
tgen_cmpi(s, ext, c, a, b);
1480
tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
1473
- tcg_out_insn(s, 3202, B_C, c, 0);
1481
+ tcg_out_insn(s, bcond_imm, B_C, c, 0);
1482
return;
1483
}
1484
@@ -1478,10 +1486,10 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,
1486
tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0);
1487
switch (c) {
1488
case TCG_COND_TSTEQ:
1481
- tcg_out_insn(s, 3205, TBZ, a, tbit, 0);
1489
+ tcg_out_insn(s, tbz, TBZ, a, tbit, 0);
1490
break;
1491
case TCG_COND_TSTNE:
1484
- tcg_out_insn(s, 3205, TBNZ, a, tbit, 0);
1492
+ tcg_out_insn(s, tbz, TBNZ, a, tbit, 0);
1493
break;
1494
default:
1495
g_assert_not_reached();
@@ -1490,10 +1498,10 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,
1498
tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
1499
switch (c) {
1500
case TCG_COND_EQ:
1493
- tcg_out_insn(s, 3201, CBZ, ext, a, 0);
1501
+ tcg_out_insn(s, cbz, CBZ, ext, a, 0);
1502
break;
1503
case TCG_COND_NE:
1496
- tcg_out_insn(s, 3201, CBNZ, ext, a, 0);
1504
+ tcg_out_insn(s, cbz, CBNZ, ext, a, 0);
1505
break;
1506
default:
1507
g_assert_not_reached();
@@ -1511,7 +1519,7 @@ static inline void tcg_out_rev(TCGContext *s, int ext, MemOp s_bits,
1519
TCGReg rd, TCGReg rn)
1520
{
1521
/* REV, REV16, REV32 */
1514
- tcg_out_insn_3507(s, I3507_REV | (s_bits << 10), ext, rd, rn);
1522
+ tcg_out_insn_rr_sf(s, Irr_sf_REV | (s_bits << 10), ext, rd, rn);
1523
}
1524
1525
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
@@ -1671,16 +1679,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1679
/* Load CPUTLBDescFast.{mask,table} into {tmp0,tmp1}. */
1680
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
1681
QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);
1674
- tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0,
1682
+ tcg_out_insn(s, ldstpair, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0,
1683
tlb_mask_table_ofs(s, mem_index), 1, 0);
1684
1685
/* Extract the TLB index from the address into X0. */
1678
- tcg_out_insn(s, 3502S, AND_LSR, TCG_TYPE_I64,
1686
+ tcg_out_insn(s, addsub_realshift, AND_LSR, TCG_TYPE_I64,
1687
TCG_REG_TMP0, TCG_REG_TMP0, addr_reg,
1688
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1689
1690
/* Add the tlb_table pointer, forming the CPUTLBEntry address. */
1683
- tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0);
1691
+ tcg_out_insn(s, addsub_shift, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1,
1692
+ TCG_REG_TMP0);
1693
1694
/* Load the tlb comparator into TMP0, and the fast path addend. */
1695
QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
@@ -1700,13 +1709,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1709
addr_adj = addr_reg;
1710
} else {
1711
addr_adj = TCG_REG_TMP2;
1703
- tcg_out_insn(s, 3401, ADDI, addr_type,
1712
+ tcg_out_insn(s, addsub_imm, ADDI, addr_type,
1713
addr_adj, addr_reg, s_mask - a_mask);
1714
}
1715
compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
1716
1717
/* Store the page mask part of the address into TMP2. */
1709
- tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_TMP2,
1718
+ tcg_out_logicali(s, Ilogic_imm_ANDI, addr_type, TCG_REG_TMP2,
1719
addr_adj, compare_mask);
1720
1721
/* Perform the address comparison. */
@@ -1714,7 +1723,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1723
1724
/* If not equal, we jump to the slow path. */
1725
ldst->label_ptr[0] = s->code_ptr;
1717
- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
1726
+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);
1727
1728
h->base = TCG_REG_TMP1;
1729
h->index = addr_reg;
@@ -1728,11 +1737,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1737
ldst->addr_reg = addr_reg;
1738
1739
/* tst addr, #mask */
1731
- tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
1740
+ tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,
1741
+ a_mask);
1742
1743
/* b.ne slow_path */
1744
ldst->label_ptr[0] = s->code_ptr;
1735
- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
1745
+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);
1746
}
1747
1748
if (guest_base || addr_type == TCG_TYPE_I32) {
@@ -1754,27 +1764,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
1764
{
1765
switch (memop & MO_SSIZE) {
1766
case MO_UB:
1757
- tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index);
1767
+ tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.index);
1768
break;
1769
case MO_SB:
1760
- tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
1770
+ tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,
1771
data_r, h.base, h.index_ext, h.index);
1772
break;
1773
case MO_UW:
1764
- tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index);
1774
+ tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.index);
1775
break;
1776
case MO_SW:
1767
- tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
1777
+ tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW),
1778
data_r, h.base, h.index_ext, h.index);
1779
break;
1780
case MO_UL:
1771
- tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index);
1781
+ tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.index);
1782
break;
1783
case MO_SL:
1774
- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.index);
1784
+ tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,
1785
+ h.index);
1786
break;
1787
case MO_UQ:
1777
- tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index);
1788
+ tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.index);
1789
break;
1790
default:
1791
g_assert_not_reached();
@@ -1786,16 +1797,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
1797
{
1798
switch (memop & MO_SIZE) {
1799
case MO_8:
1789
- tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index);
1800
+ tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.index);
1801
break;
1802
case MO_16:
1792
- tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index);
1803
+ tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.index);
1804
break;
1805
case MO_32:
1795
- tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index);
1806
+ tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.index);
1807
break;
1808
case MO_64:
1798
- tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index);
1809
+ tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.index);
1810
break;
1811
default:
1812
g_assert_not_reached();
@@ -1861,11 +1872,11 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
1872
base = TCG_REG_TMP2;
1873
if (h.index_ext == TCG_TYPE_I32) {
1874
/* add base, base, index, uxtw */
1864
- tcg_out_insn(s, 3501, ADD, TCG_TYPE_I64, base,
1875
+ tcg_out_insn(s, addsub_ext, ADD, TCG_TYPE_I64, base,
1876
h.base, h.index, MO_32, 0);
1877
} else {
1878
/* add base, base, index */
1868
- tcg_out_insn(s, 3502, ADD, 1, base, h.base, h.index);
1879
+ tcg_out_insn(s, addsub_shift, ADD, 1, base, h.base, h.index);
1880
}
1881
}
1882
@@ -1885,9 +1896,10 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
1896
* TODO: align should be MO_64, so we only need test bit 3,
1897
* which means we could use TBNZ instead of ANDS+B_C.
1898
*/
1888
- tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, 15);
1899
+ tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,
1900
+ 15);
1901
branch = s->code_ptr;
1890
- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
1902
+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);
1903
use_pair = true;
1904
}
1905
@@ -1919,22 +1931,22 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
1931
sh = datahi;
1932
}
1933
1922
- tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, ll, lh, base);
1923
- tcg_out_insn(s, 3306, STXP, TCG_REG_TMP0, sl, sh, base);
1924
- tcg_out_insn(s, 3201, CBNZ, 0, TCG_REG_TMP0, -2);
1934
+ tcg_out_insn(s, stxp, LDXP, TCG_REG_XZR, ll, lh, base);
1935
+ tcg_out_insn(s, stxp, STXP, TCG_REG_TMP0, sl, sh, base);
1936
+ tcg_out_insn(s, cbz, CBNZ, 0, TCG_REG_TMP0, -2);
1937
1938
if (use_pair) {
1939
/* "b .+8", branching across the one insn of use_pair. */
1928
- tcg_out_insn(s, 3206, B, 2);
1940
+ tcg_out_insn(s, branch, B, 2);
1941
reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr));
1942
}
1943
}
1944
1945
if (use_pair) {
1946
if (is_ld) {
1935
- tcg_out_insn(s, 3314, LDP, datalo, datahi, base, 0, 1, 0);
1947
+ tcg_out_insn(s, ldstpair, LDP, datalo, datahi, base, 0, 1, 0);
1948
} else {
1937
- tcg_out_insn(s, 3314, STP, datalo, datahi, base, 0, 1, 0);
1949
+ tcg_out_insn(s, ldstpair, STP, datalo, datahi, base, 0, 1, 0);
1950
}
1951
}
1952
@@ -1985,7 +1997,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1997
1998
offset = tcg_pcrel_diff(s, target) >> 2;
1999
if (offset == sextract64(offset, 0, 26)) {
1988
- tcg_out_insn(s, 3206, B, offset);
2000
+ tcg_out_insn(s, branch, B, offset);
2001
} else {
2002
/*
2003
* Only x16/x17 generate BTI type Jump (2),
@@ -1993,7 +2005,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
2005
*/
2006
QEMU_BUILD_BUG_ON(TCG_REG_TMP0 != TCG_REG_X16);
2007
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);
1996
- tcg_out_insn(s, 3207, BR, TCG_REG_TMP0);
2008
+ tcg_out_insn(s, bcond_reg, BR, TCG_REG_TMP0);
2009
}
2010
}
2011
@@ -2008,15 +2020,15 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
2020
tcg_debug_assert(i_off == sextract64(i_off, 0, 21));
2021
2022
set_jmp_insn_offset(s, which);
2011
- tcg_out32(s, I3206_B);
2012
- tcg_out_insn(s, 3207, BR, TCG_REG_TMP0);
2023
+ tcg_out32(s, Ibranch_B);
2024
+ tcg_out_insn(s, bcond_reg, BR, TCG_REG_TMP0);
2025
set_jmp_reset_offset(s, which);
2026
tcg_out_bti(s, BTI_J);
2027
}
2028
2029
static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
2030
{
2019
- tcg_out_insn(s, 3207, BR, a0);
2031
+ tcg_out_insn(s, bcond_reg, BR, a0);
2032
}
2033
2034
void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
@@ -2028,13 +2040,13 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2040
2041
/* Either directly branch, or indirect branch load. */
2042
if (d_offset == sextract64(d_offset, 0, 28)) {
2031
- insn = deposit32(I3206_B, 0, 26, d_offset >> 2);
2043
+ insn = deposit32(Ibranch_B, 0, 26, d_offset >> 2);
2044
} else {
2045
uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];
2046
ptrdiff_t i_offset = i_addr - jmp_rx;
2047
2048
/* Note that we asserted this in range in tcg_out_goto_tb. */
2037
- insn = deposit32(I3305_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2);
2049
+ insn = deposit32(Ildlit_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2);
2050
}
2051
qatomic_set((uint32_t *)jmp_rw, insn);
2052
flush_idcache_range(jmp_rx, jmp_rw, 4);
@@ -2044,16 +2056,16 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
2056
static void tgen_add(TCGContext *s, TCGType type,
2057
TCGReg a0, TCGReg a1, TCGReg a2)
2058
{
2047
- tcg_out_insn(s, 3502, ADD, type, a0, a1, a2);
2059
+ tcg_out_insn(s, addsub_shift, ADD, type, a0, a1, a2);
2060
}
2061
2062
static void tgen_addi(TCGContext *s, TCGType type,
2063
TCGReg a0, TCGReg a1, tcg_target_long a2)
2064
{
2065
if (a2 >= 0) {
2054
- tcg_out_insn(s, 3401, ADDI, type, a0, a1, a2);
2066
+ tcg_out_insn(s, addsub_imm, ADDI, type, a0, a1, a2);
2067
} else {
2056
- tcg_out_insn(s, 3401, SUBI, type, a0, a1, -a2);
2068
+ tcg_out_insn(s, addsub_imm, SUBI, type, a0, a1, -a2);
2069
}
2070
}
2071
@@ -2066,16 +2078,16 @@ static const TCGOutOpBinary outop_add = {
2078
static void tgen_addco(TCGContext *s, TCGType type,
2079
TCGReg a0, TCGReg a1, TCGReg a2)
2080
{
2069
- tcg_out_insn(s, 3502, ADDS, type, a0, a1, a2);
2081
+ tcg_out_insn(s, addsub_shift, ADDS, type, a0, a1, a2);
2082
}
2083
2084
static void tgen_addco_imm(TCGContext *s, TCGType type,
2085
TCGReg a0, TCGReg a1, tcg_target_long a2)
2086
{
2087
if (a2 >= 0) {
2076
- tcg_out_insn(s, 3401, ADDSI, type, a0, a1, a2);
2088
+ tcg_out_insn(s, addsub_imm, ADDSI, type, a0, a1, a2);
2089
} else {
2078
- tcg_out_insn(s, 3401, SUBSI, type, a0, a1, -a2);
2090
+ tcg_out_insn(s, addsub_imm, SUBSI, type, a0, a1, -a2);
2091
}
2092
}
2093
@@ -2088,7 +2100,7 @@ static const TCGOutOpBinary outop_addco = {
2100
static void tgen_addci_rrr(TCGContext *s, TCGType type,
2101
TCGReg a0, TCGReg a1, TCGReg a2)
2102
{
2091
- tcg_out_insn(s, 3503, ADC, type, a0, a1, a2);
2103
+ tcg_out_insn(s, rrr_sf, ADC, type, a0, a1, a2);
2104
}
2105
2106
static void tgen_addci_rri(TCGContext *s, TCGType type,
@@ -2099,9 +2111,9 @@ static void tgen_addci_rri(TCGContext *s, TCGType type,
2111
* that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa.
2112
*/
2113
if (a2) {
2102
- tcg_out_insn(s, 3503, SBC, type, a0, a1, TCG_REG_XZR);
2114
+ tcg_out_insn(s, rrr_sf, SBC, type, a0, a1, TCG_REG_XZR);
2115
} else {
2104
- tcg_out_insn(s, 3503, ADC, type, a0, a1, TCG_REG_XZR);
2116
+ tcg_out_insn(s, rrr_sf, ADC, type, a0, a1, TCG_REG_XZR);
2117
}
2118
}
2119
@@ -2114,7 +2126,7 @@ static const TCGOutOpAddSubCarry outop_addci = {
2126
static void tgen_addcio(TCGContext *s, TCGType type,
2127
TCGReg a0, TCGReg a1, TCGReg a2)
2128
{
2117
- tcg_out_insn(s, 3503, ADCS, type, a0, a1, a2);
2129
+ tcg_out_insn(s, rrr_sf, ADCS, type, a0, a1, a2);
2130
}
2131
2132
static void tgen_addcio_imm(TCGContext *s, TCGType type,
@@ -2122,9 +2134,9 @@ static void tgen_addcio_imm(TCGContext *s, TCGType type,
2134
{
2135
/* Use SBCS w/0 for ADCS w/-1 -- see above. */
2136
if (a2) {
2125
- tcg_out_insn(s, 3503, SBCS, type, a0, a1, TCG_REG_XZR);
2137
+ tcg_out_insn(s, rrr_sf, SBCS, type, a0, a1, TCG_REG_XZR);
2138
} else {
2127
- tcg_out_insn(s, 3503, ADCS, type, a0, a1, TCG_REG_XZR);
2139
+ tcg_out_insn(s, rrr_sf, ADCS, type, a0, a1, TCG_REG_XZR);
2140
}
2141
}
2142
@@ -2136,20 +2148,20 @@ static const TCGOutOpBinary outop_addcio = {
2148
2149
static void tcg_out_set_carry(TCGContext *s)
2150
{
2139
- tcg_out_insn(s, 3502, SUBS, TCG_TYPE_I32,
2151
+ tcg_out_insn(s, addsub_shift, SUBS, TCG_TYPE_I32,
2152
TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR);
2153
}
2154
2155
static void tgen_and(TCGContext *s, TCGType type,
2156
TCGReg a0, TCGReg a1, TCGReg a2)
2157
{
2146
- tcg_out_insn(s, 3510, AND, type, a0, a1, a2);
2158
+ tcg_out_insn(s, logic_shift, AND, type, a0, a1, a2);
2159
}
2160
2161
static void tgen_andi(TCGContext *s, TCGType type,
2162
TCGReg a0, TCGReg a1, tcg_target_long a2)
2163
{
2152
- tcg_out_logicali(s, I3404_ANDI, type, a0, a1, a2);
2164
+ tcg_out_logicali(s, Ilogic_imm_ANDI, type, a0, a1, a2);
2165
}
2166
2167
static const TCGOutOpBinary outop_and = {
@@ -2161,7 +2173,7 @@ static const TCGOutOpBinary outop_and = {
2173
static void tgen_andc(TCGContext *s, TCGType type,
2174
TCGReg a0, TCGReg a1, TCGReg a2)
2175
{
2164
- tcg_out_insn(s, 3510, BIC, type, a0, a1, a2);
2176
+ tcg_out_insn(s, logic_shift, BIC, type, a0, a1, a2);
2177
}
2178
2179
static const TCGOutOpBinary outop_andc = {
@@ -2173,31 +2185,31 @@ static void tgen_clz(TCGContext *s, TCGType type,
2185
TCGReg a0, TCGReg a1, TCGReg a2)
2186
{
2187
tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true);
2176
- tcg_out_insn(s, 3507, CLZ, type, TCG_REG_TMP0, a1);
2177
- tcg_out_insn(s, 3506, CSEL, type, a0, TCG_REG_TMP0, a2, TCG_COND_NE);
2188
+ tcg_out_insn(s, rr_sf, CLZ, type, TCG_REG_TMP0, a1);
2189
+ tcg_out_insn(s, csel, CSEL, type, a0, TCG_REG_TMP0, a2, TCG_COND_NE);
2190
}
2191
2192
static void tgen_clzi(TCGContext *s, TCGType type,
2193
TCGReg a0, TCGReg a1, tcg_target_long a2)
2194
{
2195
if (a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
2184
- tcg_out_insn(s, 3507, CLZ, type, a0, a1);
2196
+ tcg_out_insn(s, rr_sf, CLZ, type, a0, a1);
2197
return;
2198
}
2199
2200
tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true);
2189
- tcg_out_insn(s, 3507, CLZ, type, a0, a1);
2201
+ tcg_out_insn(s, rr_sf, CLZ, type, a0, a1);
2202
2203
switch (a2) {
2204
case -1:
2193
- tcg_out_insn(s, 3506, CSINV, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);
2205
+ tcg_out_insn(s, csel, CSINV, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);
2206
break;
2207
case 0:
2196
- tcg_out_insn(s, 3506, CSEL, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);
2208
+ tcg_out_insn(s, csel, CSEL, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);
2209
break;
2210
default:
2211
tcg_out_movi(s, type, TCG_REG_TMP0, a2);
2200
- tcg_out_insn(s, 3506, CSEL, type, a0, a0, TCG_REG_TMP0, TCG_COND_NE);
2212
+ tcg_out_insn(s, csel, CSEL, type, a0, a0, TCG_REG_TMP0, TCG_COND_NE);
2213
break;
2214
}
2215
}
@@ -2215,14 +2227,14 @@ static const TCGOutOpUnary outop_ctpop = {
2227
static void tgen_ctz(TCGContext *s, TCGType type,
2228
TCGReg a0, TCGReg a1, TCGReg a2)
2229
{
2218
- tcg_out_insn(s, 3507, RBIT, type, TCG_REG_TMP0, a1);
2230
+ tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1);
2231
tgen_clz(s, type, a0, TCG_REG_TMP0, a2);
2232
}
2233
2234
static void tgen_ctzi(TCGContext *s, TCGType type,
2235
TCGReg a0, TCGReg a1, tcg_target_long a2)
2236
{
2225
- tcg_out_insn(s, 3507, RBIT, type, TCG_REG_TMP0, a1);
2237
+ tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1);
2238
tgen_clzi(s, type, a0, TCG_REG_TMP0, a2);
2239
}
2240
@@ -2235,7 +2247,7 @@ static const TCGOutOpBinary outop_ctz = {
2247
static void tgen_divs(TCGContext *s, TCGType type,
2248
TCGReg a0, TCGReg a1, TCGReg a2)
2249
{
2238
- tcg_out_insn(s, 3508, SDIV, type, a0, a1, a2);
2250
+ tcg_out_insn(s, rrr, SDIV, type, a0, a1, a2);
2251
}
2252
2253
static const TCGOutOpBinary outop_divs = {
@@ -2250,7 +2262,7 @@ static const TCGOutOpDivRem outop_divs2 = {
2262
static void tgen_divu(TCGContext *s, TCGType type,
2263
TCGReg a0, TCGReg a1, TCGReg a2)
2264
{
2253
- tcg_out_insn(s, 3508, UDIV, type, a0, a1, a2);
2265
+ tcg_out_insn(s, rrr, UDIV, type, a0, a1, a2);
2266
}
2267
2268
static const TCGOutOpBinary outop_divu = {
@@ -2265,7 +2277,7 @@ static const TCGOutOpDivRem outop_divu2 = {
2277
static void tgen_eqv(TCGContext *s, TCGType type,
2278
TCGReg a0, TCGReg a1, TCGReg a2)
2279
{
2268
- tcg_out_insn(s, 3510, EON, type, a0, a1, a2);
2280
+ tcg_out_insn(s, logic_shift, EON, type, a0, a1, a2);
2281
}
2282
2283
static const TCGOutOpBinary outop_eqv = {
@@ -2286,7 +2298,7 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = {
2298
static void tgen_mul(TCGContext *s, TCGType type,
2299
TCGReg a0, TCGReg a1, TCGReg a2)
2300
{
2289
- tcg_out_insn(s, 3509, MADD, type, a0, a1, a2, TCG_REG_XZR);
2301
+ tcg_out_insn(s, rrrr, MADD, type, a0, a1, a2, TCG_REG_XZR);
2302
}
2303
2304
static const TCGOutOpBinary outop_mul = {
@@ -2306,7 +2318,7 @@ static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)
2318
static void tgen_mulsh(TCGContext *s, TCGType type,
2319
TCGReg a0, TCGReg a1, TCGReg a2)
2320
{
2309
- tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
2321
+ tcg_out_insn(s, rrr, SMULH, TCG_TYPE_I64, a0, a1, a2);
2322
}
2323
2324
static const TCGOutOpBinary outop_mulsh = {
@@ -2322,7 +2334,7 @@ static const TCGOutOpMul2 outop_mulu2 = {
2334
static void tgen_muluh(TCGContext *s, TCGType type,
2335
TCGReg a0, TCGReg a1, TCGReg a2)
2336
{
2325
- tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
2337
+ tcg_out_insn(s, rrr, UMULH, TCG_TYPE_I64, a0, a1, a2);
2338
}
2339
2340
static const TCGOutOpBinary outop_muluh = {
@@ -2342,13 +2354,13 @@ static const TCGOutOpBinary outop_nor = {
2354
static void tgen_or(TCGContext *s, TCGType type,
2355
TCGReg a0, TCGReg a1, TCGReg a2)
2356
{
2345
- tcg_out_insn(s, 3510, ORR, type, a0, a1, a2);
2357
+ tcg_out_insn(s, logic_shift, ORR, type, a0, a1, a2);
2358
}
2359
2360
static void tgen_ori(TCGContext *s, TCGType type,
2361
TCGReg a0, TCGReg a1, tcg_target_long a2)
2362
{
2351
- tcg_out_logicali(s, I3404_ORRI, type, a0, a1, a2);
2363
+ tcg_out_logicali(s, Ilogic_imm_ORRI, type, a0, a1, a2);
2364
}
2365
2366
static const TCGOutOpBinary outop_or = {
@@ -2360,7 +2372,7 @@ static const TCGOutOpBinary outop_or = {
2372
static void tgen_orc(TCGContext *s, TCGType type,
2373
TCGReg a0, TCGReg a1, TCGReg a2)
2374
{
2363
- tcg_out_insn(s, 3510, ORN, type, a0, a1, a2);
2375
+ tcg_out_insn(s, logic_shift, ORN, type, a0, a1, a2);
2376
}
2377
2378
static const TCGOutOpBinary outop_orc = {
@@ -2371,8 +2383,8 @@ static const TCGOutOpBinary outop_orc = {
2383
static void tgen_rems(TCGContext *s, TCGType type,
2384
TCGReg a0, TCGReg a1, TCGReg a2)
2385
{
2374
- tcg_out_insn(s, 3508, SDIV, type, TCG_REG_TMP0, a1, a2);
2375
- tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1);
2386
+ tcg_out_insn(s, rrr, SDIV, type, TCG_REG_TMP0, a1, a2);
2387
+ tcg_out_insn(s, rrrr, MSUB, type, a0, TCG_REG_TMP0, a2, a1);
2388
}
2389
2390
static const TCGOutOpBinary outop_rems = {
@@ -2383,8 +2395,8 @@ static const TCGOutOpBinary outop_rems = {
2395
static void tgen_remu(TCGContext *s, TCGType type,
2396
TCGReg a0, TCGReg a1, TCGReg a2)
2397
{
2386
- tcg_out_insn(s, 3508, UDIV, type, TCG_REG_TMP0, a1, a2);
2387
- tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1);
2398
+ tcg_out_insn(s, rrr, UDIV, type, TCG_REG_TMP0, a1, a2);
2399
+ tcg_out_insn(s, rrrr, MSUB, type, a0, TCG_REG_TMP0, a2, a1);
2400
}
2401
2402
static const TCGOutOpBinary outop_remu = {
@@ -2399,7 +2411,7 @@ static const TCGOutOpBinary outop_rotl = {
2411
static void tgen_rotr(TCGContext *s, TCGType type,
2412
TCGReg a0, TCGReg a1, TCGReg a2)
2413
{
2402
- tcg_out_insn(s, 3508, RORV, type, a0, a1, a2);
2414
+ tcg_out_insn(s, rrr, RORV, type, a0, a1, a2);
2415
}
2416
2417
static void tgen_rotri(TCGContext *s, TCGType type,
@@ -2418,7 +2430,7 @@ static const TCGOutOpBinary outop_rotr = {
2430
static void tgen_sar(TCGContext *s, TCGType type,
2431
TCGReg a0, TCGReg a1, TCGReg a2)
2432
{
2421
- tcg_out_insn(s, 3508, ASRV, type, a0, a1, a2);
2433
+ tcg_out_insn(s, rrr, ASRV, type, a0, a1, a2);
2434
}
2435
2436
static void tgen_sari(TCGContext *s, TCGType type,
@@ -2437,7 +2449,7 @@ static const TCGOutOpBinary outop_sar = {
2449
static void tgen_shl(TCGContext *s, TCGType type,
2450
TCGReg a0, TCGReg a1, TCGReg a2)
2451
{
2440
- tcg_out_insn(s, 3508, LSLV, type, a0, a1, a2);
2452
+ tcg_out_insn(s, rrr, LSLV, type, a0, a1, a2);
2453
}
2454
2455
static void tgen_shli(TCGContext *s, TCGType type,
@@ -2456,7 +2468,7 @@ static const TCGOutOpBinary outop_shl = {
2468
static void tgen_shr(TCGContext *s, TCGType type,
2469
TCGReg a0, TCGReg a1, TCGReg a2)
2470
{
2459
- tcg_out_insn(s, 3508, LSRV, type, a0, a1, a2);
2471
+ tcg_out_insn(s, rrr, LSRV, type, a0, a1, a2);
2472
}
2473
2474
static void tgen_shri(TCGContext *s, TCGType type,
@@ -2475,7 +2487,7 @@ static const TCGOutOpBinary outop_shr = {
2487
static void tgen_sub(TCGContext *s, TCGType type,
2488
TCGReg a0, TCGReg a1, TCGReg a2)
2489
{
2478
- tcg_out_insn(s, 3502, SUB, type, a0, a1, a2);
2490
+ tcg_out_insn(s, addsub_shift, SUB, type, a0, a1, a2);
2491
}
2492
2493
static const TCGOutOpSubtract outop_sub = {
@@ -2486,16 +2498,16 @@ static const TCGOutOpSubtract outop_sub = {
2498
static void tgen_subbo_rrr(TCGContext *s, TCGType type,
2499
TCGReg a0, TCGReg a1, TCGReg a2)
2500
{
2489
- tcg_out_insn(s, 3502, SUBS, type, a0, a1, a2);
2501
+ tcg_out_insn(s, addsub_shift, SUBS, type, a0, a1, a2);
2502
}
2503
2504
static void tgen_subbo_rri(TCGContext *s, TCGType type,
2505
TCGReg a0, TCGReg a1, tcg_target_long a2)
2506
{
2507
if (a2 >= 0) {
2496
- tcg_out_insn(s, 3401, SUBSI, type, a0, a1, a2);
2508
+ tcg_out_insn(s, addsub_imm, SUBSI, type, a0, a1, a2);
2509
} else {
2498
- tcg_out_insn(s, 3401, ADDSI, type, a0, a1, -a2);
2510
+ tcg_out_insn(s, addsub_imm, ADDSI, type, a0, a1, -a2);
2511
}
2512
}
2513
@@ -2535,7 +2547,7 @@ static const TCGOutOpAddSubCarry outop_subbo = {
2547
static void tgen_subbi_rrr(TCGContext *s, TCGType type,
2548
TCGReg a0, TCGReg a1, TCGReg a2)
2549
{
2538
- tcg_out_insn(s, 3503, SBC, type, a0, a1, a2);
2550
+ tcg_out_insn(s, rrr_sf, SBC, type, a0, a1, a2);
2551
}
2552
2553
static void tgen_subbi_rri(TCGContext *s, TCGType type,
@@ -2553,7 +2565,7 @@ static const TCGOutOpAddSubCarry outop_subbi = {
2565
static void tgen_subbio_rrr(TCGContext *s, TCGType type,
2566
TCGReg a0, TCGReg a1, TCGReg a2)
2567
{
2556
- tcg_out_insn(s, 3503, SBCS, type, a0, a1, a2);
2568
+ tcg_out_insn(s, rrr_sf, SBCS, type, a0, a1, a2);
2569
}
2570
2571
static void tgen_subbio_rri(TCGContext *s, TCGType type,
@@ -2570,20 +2582,20 @@ static const TCGOutOpAddSubCarry outop_subbio = {
2582
2583
static void tcg_out_set_borrow(TCGContext *s)
2584
{
2573
- tcg_out_insn(s, 3502, ADDS, TCG_TYPE_I32,
2585
+ tcg_out_insn(s, addsub_shift, ADDS, TCG_TYPE_I32,
2586
TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR);
2587
}
2588
2589
static void tgen_xor(TCGContext *s, TCGType type,
2590
TCGReg a0, TCGReg a1, TCGReg a2)
2591
{
2580
- tcg_out_insn(s, 3510, EOR, type, a0, a1, a2);
2592
+ tcg_out_insn(s, logic_shift, EOR, type, a0, a1, a2);
2593
}
2594
2595
static void tgen_xori(TCGContext *s, TCGType type,
2596
TCGReg a0, TCGReg a1, tcg_target_long a2)
2597
{
2586
- tcg_out_logicali(s, I3404_EORI, type, a0, a1, a2);
2598
+ tcg_out_logicali(s, Ilogic_imm_EORI, type, a0, a1, a2);
2599
}
2600
2601
static const TCGOutOpBinary outop_xor = {
@@ -2657,7 +2669,7 @@ static const TCGOutOpUnary outop_not = {
2669
static void tgen_cset(TCGContext *s, TCGCond cond, TCGReg ret)
2670
{
2671
/* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
2660
- tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, ret, TCG_REG_XZR,
2672
+ tcg_out_insn(s, csel, CSINC, TCG_TYPE_I32, ret, TCG_REG_XZR,
2673
TCG_REG_XZR, tcg_invert_cond(cond));
2674
}
2675
@@ -2684,7 +2696,7 @@ static const TCGOutOpSetcond outop_setcond = {
2696
static void tgen_csetm(TCGContext *s, TCGType ext, TCGCond cond, TCGReg ret)
2697
{
2698
/* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */
2687
- tcg_out_insn(s, 3506, CSINV, ext, ret, TCG_REG_XZR,
2699
+ tcg_out_insn(s, csel, CSINV, ext, ret, TCG_REG_XZR,
2700
TCG_REG_XZR, tcg_invert_cond(cond));
2701
}
2702
@@ -2713,7 +2725,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond,
2725
TCGArg vt, bool const_vt, TCGArg vf, bool const_vf)
2726
{
2727
tcg_out_cmp(s, type, cond, c1, c2, const_c2);
2716
- tcg_out_insn(s, 3506, CSEL, type, ret, vt, vf, cond);
2728
+ tcg_out_insn(s, csel, CSEL, type, ret, vt, vf, cond);
2729
}
2730
2731
static const TCGOutOpMovcond outop_movcond = {
@@ -2765,7 +2777,7 @@ static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
2777
{
2778
if (ofs == 0) {
2779
uint64_t mask = MAKE_64BIT_MASK(0, len);
2768
- tcg_out_logicali(s, I3404_ANDI, type, a0, a1, mask);
2780
+ tcg_out_logicali(s, Ilogic_imm_ANDI, type, a0, a1, mask);
2781
} else {
2782
tcg_out_ubfm(s, type, a0, a1, ofs, ofs + len - 1);
2783
}
@@ -2801,7 +2813,7 @@ static const TCGOutOpExtract2 outop_extract2 = {
2813
static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest,
2814
TCGReg base, ptrdiff_t offset)
2815
{
2804
- tcg_out_ldst(s, I3312_LDRB, dest, base, offset, 0);
2816
+ tcg_out_ldst(s, Ildst_imm_LDRB, dest, base, offset, 0);
2817
}
2818
2819
static const TCGOutOpLoad outop_ld8u = {
@@ -2812,7 +2824,8 @@ static const TCGOutOpLoad outop_ld8u = {
2824
static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest,
2825
TCGReg base, ptrdiff_t offset)
2826
{
2815
- AArch64Insn insn = type == TCG_TYPE_I32 ? I3312_LDRSBW : I3312_LDRSBX;
2827
+ AArch64Insn insn = type == TCG_TYPE_I32 ? Ildst_imm_LDRSBW
2828
+ : Ildst_imm_LDRSBX;
2829
tcg_out_ldst(s, insn, dest, base, offset, 0);
2830
}
2831
@@ -2824,7 +2837,7 @@ static const TCGOutOpLoad outop_ld8s = {
2837
static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest,
2838
TCGReg base, ptrdiff_t offset)
2839
{
2827
- tcg_out_ldst(s, I3312_LDRH, dest, base, offset, 1);
2840
+ tcg_out_ldst(s, Ildst_imm_LDRH, dest, base, offset, 1);
2841
}
2842
2843
static const TCGOutOpLoad outop_ld16u = {
@@ -2835,7 +2848,8 @@ static const TCGOutOpLoad outop_ld16u = {
2848
static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest,
2849
TCGReg base, ptrdiff_t offset)
2850
{
2838
- AArch64Insn insn = type == TCG_TYPE_I32 ? I3312_LDRSHW : I3312_LDRSHX;
2851
+ AArch64Insn insn = type == TCG_TYPE_I32 ? Ildst_imm_LDRSHW
2852
+ : Ildst_imm_LDRSHX;
2853
tcg_out_ldst(s, insn, dest, base, offset, 1);
2854
}
2855
@@ -2847,7 +2861,7 @@ static const TCGOutOpLoad outop_ld16s = {
2861
static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest,
2862
TCGReg base, ptrdiff_t offset)
2863
{
2850
- tcg_out_ldst(s, I3312_LDRW, dest, base, offset, 2);
2864
+ tcg_out_ldst(s, Ildst_imm_LDRW, dest, base, offset, 2);
2865
}
2866
2867
static const TCGOutOpLoad outop_ld32u = {
@@ -2858,7 +2872,7 @@ static const TCGOutOpLoad outop_ld32u = {
2872
static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest,
2873
TCGReg base, ptrdiff_t offset)
2874
{
2861
- tcg_out_ldst(s, I3312_LDRSWX, dest, base, offset, 2);
2875
+ tcg_out_ldst(s, Ildst_imm_LDRSWX, dest, base, offset, 2);
2876
}
2877
2878
static const TCGOutOpLoad outop_ld32s = {
@@ -2869,7 +2883,7 @@ static const TCGOutOpLoad outop_ld32s = {
2883
static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
2884
TCGReg base, ptrdiff_t offset)
2885
{
2872
- tcg_out_ldst(s, I3312_STRB, data, base, offset, 0);
2886
+ tcg_out_ldst(s, Ildst_imm_STRB, data, base, offset, 0);
2887
}
2888
2889
static const TCGOutOpStore outop_st8 = {
@@ -2880,7 +2894,7 @@ static const TCGOutOpStore outop_st8 = {
2894
static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,
2895
TCGReg base, ptrdiff_t offset)
2896
{
2883
- tcg_out_ldst(s, I3312_STRH, data, base, offset, 1);
2897
+ tcg_out_ldst(s, Ildst_imm_STRH, data, base, offset, 1);
2898
}
2899
2900
static const TCGOutOpStore outop_st16 = {
@@ -2899,32 +2913,32 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
2913
const int const_args[TCG_MAX_OP_ARGS])
2914
{
2915
static const AArch64Insn cmp_vec_insn[16] = {
2902
- [TCG_COND_EQ] = I3616_CMEQ,
2903
- [TCG_COND_GT] = I3616_CMGT,
2904
- [TCG_COND_GE] = I3616_CMGE,
2905
- [TCG_COND_GTU] = I3616_CMHI,
2906
- [TCG_COND_GEU] = I3616_CMHS,
2916
+ [TCG_COND_EQ] = Iqrrr_e_CMEQ,
2917
+ [TCG_COND_GT] = Iqrrr_e_CMGT,
2918
+ [TCG_COND_GE] = Iqrrr_e_CMGE,
2919
+ [TCG_COND_GTU] = Iqrrr_e_CMHI,
2920
+ [TCG_COND_GEU] = Iqrrr_e_CMHS,
2921
};
2922
static const AArch64Insn cmp_scalar_insn[16] = {
2909
- [TCG_COND_EQ] = I3611_CMEQ,
2910
- [TCG_COND_GT] = I3611_CMGT,
2911
- [TCG_COND_GE] = I3611_CMGE,
2912
- [TCG_COND_GTU] = I3611_CMHI,
2913
- [TCG_COND_GEU] = I3611_CMHS,
2923
+ [TCG_COND_EQ] = Irrr_e_CMEQ,
2924
+ [TCG_COND_GT] = Irrr_e_CMGT,
2925
+ [TCG_COND_GE] = Irrr_e_CMGE,
2926
+ [TCG_COND_GTU] = Irrr_e_CMHI,
2927
+ [TCG_COND_GEU] = Irrr_e_CMHS,
2928
};
2929
static const AArch64Insn cmp0_vec_insn[16] = {
2916
- [TCG_COND_EQ] = I3617_CMEQ0,
2917
- [TCG_COND_GT] = I3617_CMGT0,
2918
- [TCG_COND_GE] = I3617_CMGE0,
2919
- [TCG_COND_LT] = I3617_CMLT0,
2920
- [TCG_COND_LE] = I3617_CMLE0,
2930
+ [TCG_COND_EQ] = Iqrr_e_CMEQ0,
2931
+ [TCG_COND_GT] = Iqrr_e_CMGT0,
2932
+ [TCG_COND_GE] = Iqrr_e_CMGE0,
2933
+ [TCG_COND_LT] = Iqrr_e_CMLT0,
2934
+ [TCG_COND_LE] = Iqrr_e_CMLE0,
2935
};
2936
static const AArch64Insn cmp0_scalar_insn[16] = {
2923
- [TCG_COND_EQ] = I3612_CMEQ0,
2924
- [TCG_COND_GT] = I3612_CMGT0,
2925
- [TCG_COND_GE] = I3612_CMGE0,
2926
- [TCG_COND_LT] = I3612_CMLT0,
2927
- [TCG_COND_LE] = I3612_CMLE0,
2937
+ [TCG_COND_EQ] = Isimd_rr_CMEQ0,
2938
+ [TCG_COND_GT] = Isimd_rr_CMGT0,
2939
+ [TCG_COND_GE] = Isimd_rr_CMGE0,
2940
+ [TCG_COND_LT] = Isimd_rr_CMLT0,
2941
+ [TCG_COND_LE] = Isimd_rr_CMLE0,
2942
};
2943
2944
TCGType type = vecl + TCG_TYPE_V64;
@@ -2949,169 +2963,173 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
2963
break;
2964
case INDEX_op_add_vec:
2965
if (is_scalar) {
2952
- tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2);
2966
+ tcg_out_insn(s, rrr_e, ADD, vece, a0, a1, a2);
2967
} else {
2954
- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
2968
+ tcg_out_insn(s, qrrr_e, ADD, is_q, vece, a0, a1, a2);
2969
}
2970
break;
2971
case INDEX_op_sub_vec:
2972
if (is_scalar) {
2959
- tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2);
2973
+ tcg_out_insn(s, rrr_e, SUB, vece, a0, a1, a2);
2974
} else {
2961
- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
2975
+ tcg_out_insn(s, qrrr_e, SUB, is_q, vece, a0, a1, a2);
2976
}
2977
break;
2978
case INDEX_op_mul_vec:
2965
- tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
2979
+ tcg_out_insn(s, qrrr_e, MUL, is_q, vece, a0, a1, a2);
2980
break;
2981
case INDEX_op_neg_vec:
2982
if (is_scalar) {
2969
- tcg_out_insn(s, 3612, NEG, vece, a0, a1);
2983
+ tcg_out_insn(s, simd_rr, NEG, vece, a0, a1);
2984
} else {
2971
- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
2985
+ tcg_out_insn(s, qrr_e, NEG, is_q, vece, a0, a1);
2986
}
2987
break;
2988
case INDEX_op_abs_vec:
2989
if (is_scalar) {
2976
- tcg_out_insn(s, 3612, ABS, vece, a0, a1);
2990
+ tcg_out_insn(s, simd_rr, ABS, vece, a0, a1);
2991
} else {
2978
- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);
2992
+ tcg_out_insn(s, qrr_e, ABS, is_q, vece, a0, a1);
2993
}
2994
break;
2995
case INDEX_op_and_vec:
2996
if (const_args[2]) {
2997
is_shimm1632(~a2, &cmode, &imm8);
2998
if (a0 == a1) {
2985
- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
2999
+ tcg_out_insn(s, simd_imm, BIC, is_q, a0, 0, cmode, imm8);
3000
return;
3001
}
2988
- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
3002
+ tcg_out_insn(s, simd_imm, MVNI, is_q, a0, 0, cmode, imm8);
3003
a2 = a0;
3004
}
2991
- tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
3005
+ tcg_out_insn(s, qrrr_e, AND, is_q, 0, a0, a1, a2);
3006
break;
3007
case INDEX_op_or_vec:
3008
if (const_args[2]) {
3009
is_shimm1632(a2, &cmode, &imm8);
3010
if (a0 == a1) {
2997
- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
3011
+ tcg_out_insn(s, simd_imm, ORR, is_q, a0, 0, cmode, imm8);
3012
return;
3013
}
3000
- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
3014
+ tcg_out_insn(s, simd_imm, MOVI, is_q, a0, 0, cmode, imm8);
3015
a2 = a0;
3016
}
3003
- tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
3017
+ tcg_out_insn(s, qrrr_e, ORR, is_q, 0, a0, a1, a2);
3018
break;
3019
case INDEX_op_andc_vec:
3020
if (const_args[2]) {
3021
is_shimm1632(a2, &cmode, &imm8);
3022
if (a0 == a1) {
3009
- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);
3023
+ tcg_out_insn(s, simd_imm, BIC, is_q, a0, 0, cmode, imm8);
3024
return;
3025
}
3012
- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);
3026
+ tcg_out_insn(s, simd_imm, MOVI, is_q, a0, 0, cmode, imm8);
3027
a2 = a0;
3028
}
3015
- tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
3029
+ tcg_out_insn(s, qrrr_e, BIC, is_q, 0, a0, a1, a2);
3030
break;
3031
case INDEX_op_orc_vec:
3032
if (const_args[2]) {
3033
is_shimm1632(~a2, &cmode, &imm8);
3034
if (a0 == a1) {
3021
- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);
3035
+ tcg_out_insn(s, simd_imm, ORR, is_q, a0, 0, cmode, imm8);
3036
return;
3037
}
3024
- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);
3038
+ tcg_out_insn(s, simd_imm, MVNI, is_q, a0, 0, cmode, imm8);
3039
a2 = a0;
3040
}
3027
- tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
3041
+ tcg_out_insn(s, qrrr_e, ORN, is_q, 0, a0, a1, a2);
3042
break;
3043
case INDEX_op_xor_vec:
3030
- tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
3044
+ tcg_out_insn(s, qrrr_e, EOR, is_q, 0, a0, a1, a2);
3045
break;
3046
case INDEX_op_ssadd_vec:
3047
if (is_scalar) {
3034
- tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2);
3048
+ tcg_out_insn(s, rrr_e, SQADD, vece, a0, a1, a2);
3049
} else {
3036
- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);
3050
+ tcg_out_insn(s, qrrr_e, SQADD, is_q, vece, a0, a1, a2);
3051
}
3052
break;
3053
case INDEX_op_sssub_vec:
3054
if (is_scalar) {
3041
- tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2);
3055
+ tcg_out_insn(s, rrr_e, SQSUB, vece, a0, a1, a2);
3056
} else {
3043
- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);
3057
+ tcg_out_insn(s, qrrr_e, SQSUB, is_q, vece, a0, a1, a2);
3058
}
3059
break;
3060
case INDEX_op_usadd_vec:
3061
if (is_scalar) {
3048
- tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2);
3062
+ tcg_out_insn(s, rrr_e, UQADD, vece, a0, a1, a2);
3063
} else {
3050
- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);
3064
+ tcg_out_insn(s, qrrr_e, UQADD, is_q, vece, a0, a1, a2);
3065
}
3066
break;
3067
case INDEX_op_ussub_vec:
3068
if (is_scalar) {
3055
- tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2);
3069
+ tcg_out_insn(s, rrr_e, UQSUB, vece, a0, a1, a2);
3070
} else {
3057
- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);
3071
+ tcg_out_insn(s, qrrr_e, UQSUB, is_q, vece, a0, a1, a2);
3072
}
3073
break;
3074
case INDEX_op_smax_vec:
3061
- tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);
3075
+ tcg_out_insn(s, qrrr_e, SMAX, is_q, vece, a0, a1, a2);
3076
break;
3077
case INDEX_op_smin_vec:
3064
- tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);
3078
+ tcg_out_insn(s, qrrr_e, SMIN, is_q, vece, a0, a1, a2);
3079
break;
3080
case INDEX_op_umax_vec:
3067
- tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);
3081
+ tcg_out_insn(s, qrrr_e, UMAX, is_q, vece, a0, a1, a2);
3082
break;
3083
case INDEX_op_umin_vec:
3070
- tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);
3084
+ tcg_out_insn(s, qrrr_e, UMIN, is_q, vece, a0, a1, a2);
3085
break;
3086
case INDEX_op_not_vec:
3073
- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
3087
+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a1);
3088
break;
3089
case INDEX_op_shli_vec:
3090
if (is_scalar) {
3077
- tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece));
3091
+ tcg_out_insn(s, q_shift, SHL, a0, a1, a2 + (8 << vece));
3092
} else {
3079
- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
3093
+ tcg_out_insn(s, simd_shift_imm, SHL, is_q, a0, a1,
3094
+ a2 + (8 << vece));
3095
}
3096
break;
3097
case INDEX_op_shri_vec:
3098
if (is_scalar) {
3084
- tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2);
3099
+ tcg_out_insn(s, q_shift, USHR, a0, a1, (16 << vece) - a2);
3100
} else {
3086
- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
3101
+ tcg_out_insn(s, simd_shift_imm, USHR, is_q, a0, a1,
3102
+ (16 << vece) - a2);
3103
}
3104
break;
3105
case INDEX_op_sari_vec:
3106
if (is_scalar) {
3091
- tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2);
3107
+ tcg_out_insn(s, q_shift, SSHR, a0, a1, (16 << vece) - a2);
3108
} else {
3093
- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
3109
+ tcg_out_insn(s, simd_shift_imm, SSHR, is_q, a0, a1,
3110
+ (16 << vece) - a2);
3111
}
3112
break;
3113
case INDEX_op_aa64_sli_vec:
3114
if (is_scalar) {
3098
- tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece));
3115
+ tcg_out_insn(s, q_shift, SLI, a0, a2, args[3] + (8 << vece));
3116
} else {
3100
- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));
3117
+ tcg_out_insn(s, simd_shift_imm, SLI, is_q, a0, a2,
3118
+ args[3] + (8 << vece));
3119
}
3120
break;
3121
case INDEX_op_shlv_vec:
3122
if (is_scalar) {
3105
- tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2);
3123
+ tcg_out_insn(s, rrr_e, USHL, vece, a0, a1, a2);
3124
} else {
3107
- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);
3125
+ tcg_out_insn(s, qrrr_e, USHL, is_q, vece, a0, a1, a2);
3126
}
3127
break;
3128
case INDEX_op_aa64_sshl_vec:
3129
if (is_scalar) {
3112
- tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2);
3130
+ tcg_out_insn(s, rrr_e, SSHL, vece, a0, a1, a2);
3131
} else {
3114
- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);
3132
+ tcg_out_insn(s, qrrr_e, SSHL, is_q, vece, a0, a1, a2);
3133
}
3134
break;
3135
case INDEX_op_cmp_vec:
@@ -3123,17 +3141,17 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3141
case TCG_COND_NE:
3142
if (const_args[2]) {
3143
if (is_scalar) {
3126
- tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
3144
+ tcg_out_insn(s, rrr_e, CMTST, vece, a0, a1, a1);
3145
} else {
3128
- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
3146
+ tcg_out_insn(s, qrrr_e, CMTST, is_q, vece, a0, a1, a1);
3147
}
3148
} else {
3149
if (is_scalar) {
3132
- tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2);
3150
+ tcg_out_insn(s, rrr_e, CMEQ, vece, a0, a1, a2);
3151
} else {
3134
- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
3152
+ tcg_out_insn(s, qrrr_e, CMEQ, is_q, vece, a0, a1, a2);
3153
}
3136
- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
3154
+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a0);
3155
}
3156
break;
3157
@@ -3146,12 +3164,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3164
break;
3165
}
3166
if (is_scalar) {
3149
- tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);
3167
+ tcg_out_insn(s, rrr_e, CMTST, vece, a0, a1, a2);
3168
} else {
3151
- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);
3169
+ tcg_out_insn(s, qrrr_e, CMTST, is_q, vece, a0, a1, a2);
3170
}
3171
if (cond == TCG_COND_TSTEQ) {
3154
- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
3172
+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a0);
3173
}
3174
break;
3175
@@ -3160,13 +3178,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3178
if (is_scalar) {
3179
insn = cmp0_scalar_insn[cond];
3180
if (insn) {
3163
- tcg_out_insn_3612(s, insn, vece, a0, a1);
3181
+ tcg_out_insn_simd_rr(s, insn, vece, a0, a1);
3182
break;
3183
}
3184
} else {
3185
insn = cmp0_vec_insn[cond];
3186
if (insn) {
3169
- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
3187
+ tcg_out_insn_qrr_e(s, insn, is_q, vece, a0, a1);
3188
break;
3189
}
3190
}
@@ -3182,7 +3200,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3200
insn = cmp_scalar_insn[cond];
3201
tcg_debug_assert(insn != 0);
3202
}
3185
- tcg_out_insn_3611(s, insn, vece, a0, a1, a2);
3203
+ tcg_out_insn_rrr_e(s, insn, vece, a0, a1, a2);
3204
} else {
3205
insn = cmp_vec_insn[cond];
3206
if (insn == 0) {
@@ -3192,7 +3210,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3210
insn = cmp_vec_insn[cond];
3211
tcg_debug_assert(insn != 0);
3212
}
3195
- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
3213
+ tcg_out_insn_qrrr_e(s, insn, is_q, vece, a0, a1, a2);
3214
}
3215
break;
3216
}
@@ -3202,14 +3220,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
3220
case INDEX_op_bitsel_vec:
3221
a3 = args[3];
3222
if (a0 == a3) {
3205
- tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1);
3223
+ tcg_out_insn(s, qrrr_e, BIT, is_q, 0, a0, a2, a1);
3224
} else if (a0 == a2) {
3207
- tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1);
3225
+ tcg_out_insn(s, qrrr_e, BIF, is_q, 0, a0, a3, a1);
3226
} else {
3227
if (a0 != a1) {
3228
tcg_out_mov(s, type, a0, a1);
3229
}
3212
- tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3);
3230
+ tcg_out_insn(s, qrrr_e, BSL, is_q, 0, a0, a2, a3);
3231
}
3232
break;
3233
@@ -3447,7 +3465,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
3465
tcg_out_bti(s, BTI_C);
3466
3467
/* Push (FP, LR) and allocate space for all saved registers. */
3450
- tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR,
3468
+ tcg_out_insn(s, ldstpair, STP, TCG_REG_FP, TCG_REG_LR,
3469
TCG_REG_SP, -PUSH_SIZE, 1, 1);
3470
3471
/* Set up frame pointer for canonical unwinding. */
@@ -3456,11 +3474,11 @@ static void tcg_target_qemu_prologue(TCGContext *s)
3474
/* Store callee-preserved regs x19..x28. */
3475
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
3476
int ofs = (r - TCG_REG_X19 + 2) * 8;
3459
- tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3477
+ tcg_out_insn(s, ldstpair, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3478
}
3479
3480
/* Make stack space for TCG locals. */
3463
- tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
3481
+ tcg_out_insn(s, addsub_imm, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
3482
FRAME_SIZE - PUSH_SIZE);
3483
3484
/* Inform TCG about how to find TCG locals with register, offset, size. */
@@ -3479,7 +3497,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
3497
}
3498
3499
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
3482
- tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);
3500
+ tcg_out_insn(s, bcond_reg, BR, tcg_target_call_iarg_regs[1]);
3501
3502
/*
3503
* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
@@ -3494,19 +3512,19 @@ static void tcg_target_qemu_prologue(TCGContext *s)
3512
tcg_out_bti(s, BTI_J);
3513
3514
/* Remove TCG locals stack space. */
3497
- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
3515
+ tcg_out_insn(s, addsub_imm, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
3516
FRAME_SIZE - PUSH_SIZE);
3517
3518
/* Restore registers x19..x28. */
3519
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
3520
int ofs = (r - TCG_REG_X19 + 2) * 8;
3503
- tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3521
+ tcg_out_insn(s, ldstpair, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
3522
}
3523
3524
/* Pop (FP, LR), restore SP to previous frame. */
3507
- tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR,
3525
+ tcg_out_insn(s, ldstpair, LDP, TCG_REG_FP, TCG_REG_LR,
3526
TCG_REG_SP, PUSH_SIZE, 0, 1);
3509
- tcg_out_insn(s, 3207, RET, TCG_REG_LR);
3527
+ tcg_out_insn(s, bcond_reg, RET, TCG_REG_LR);
3528
}
3529
3530
static void tcg_out_tb_start(TCGContext *s)