target/arm/cpu.h: New GPCCR fields
Add SA, NSP, NA6, NA7 for GDI and GPCBW for good measure. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org> Message-id: 20260421-jmac-feat_rme_gdi-v3-2-ecd20c77eae1@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jim MacArthur committed
May 5, 2026 at 09:25 UTC
9c8acbcd64851ffac4559b0de58295564621a306
1 file changed
+5
target/arm/cpu.h
+5
@@ -2091,6 +2091,11 @@ FIELD(GPCCR, TBGPCD, 18, 1)
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FIELD(GPCCR, NSO, 19, 1)
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FIELD(GPCCR, L0GPTSZ, 20, 4)
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FIELD(GPCCR, APPSAA, 24, 1)
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+FIELD(GPCCR, SA, 25, 1)
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+FIELD(GPCCR, NSP, 26, 1)
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+FIELD(GPCCR, NA6, 27, 1)
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+FIELD(GPCCR, NA7, 28, 1)
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+FIELD(GPCCR, GPCBW, 29, 1)
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FIELD(MFAR, FPA, 12, 40)
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FIELD(MFAR, NSE, 62, 1)