target/mips: expose Octeon68XX floating-point support
Octeon68XX cores implement CP1. Advertise that in the CPU definition by setting Config1.FP, enabling the writable Status bits, and providing the FCR0/FCR31 defaults used by this CPU model. This lets guests observe the expected floating-point feature bits and use CP1 with -cpu Octeon68XX. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-5-philmd@linaro.org>
James Hilliard committed
Apr 11, 2026 at 01:06 UTC
9e64b41b4d28f9d59c2da0b922308d6df27ab0b0
1 file changed
+8
-2
target/mips/cpu-defs.c.inc
+8
-2
@@ -997,7 +997,8 @@ const mips_def_t mips_defs[] =
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.CP0_PRid = 0x000D9100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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- .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
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+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) |
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+ (0x3F << CP0C1_MMU) |
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(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
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(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
@@ -1011,7 +1012,12 @@ const mips_def_t mips_defs[] =
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.CP0_PageGrain = (1 << CP0PG_ELPA),
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.SYNCI_Step = 32,
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.CCRes = 2,
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- .CP0_Status_rw_bitmask = 0x12F8FFFF,
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+ .CP0_Status_rw_bitmask = 0x36F8FFFF,
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+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
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+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
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+ (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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+ .CP1_fcr31 = 0,
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+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
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.SEGBITS = 42,
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.PABITS = 49,
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.insn_flags = CPU_MIPS64R2 | INSN_OCTEON,