target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1
Implement ICC_HPPIR_EL1, which the guest can use to read the current highest priority pending interrupt. Like APR, PCR and CR0, this is banked, with the _EL1 register reading the answer for the current logical interrupt domain, and the _EL3 register reading the answer for the EL3 interrupt domain. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-47-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
9edad4ff31cbb2f1e46e80e8f33699a5a387201f
3 files changed
+84
hw/intc/arm_gicv5.c
+10
@@ -527,6 +527,16 @@ static void irs_recall_hppis(GICv5 *s, GICv5Domain domain)
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}
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}
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+GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain,
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+ uint32_t iaffid)
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+{
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+ GICv5 *s = ARM_GICV5(cs);
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+ int cpuidx = irs_cpuidx_from_iaffid(cs, iaffid);
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+
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+ assert(cpuidx >= 0);
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+ return s->hppi[domain][cpuidx];
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+}
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+
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static hwaddr l1_iste_addr(GICv5Common *cs, const GICv5ISTConfig *cfg,
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uint32_t id)
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{
include/hw/intc/arm_gicv5_stream.h
+13
@@ -175,4 +175,17 @@ uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,
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*/
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void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain);
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+/**
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+ * gicv5_get_hppi
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+ * @cs: GIC IRS to query
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+ * @domain: interrupt domain to act on
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+ * @iaffid: IAFFID of this CPU interface
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+ *
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+ * Ask the IRS for the highest priority pending interrupt that it has
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+ * for this CPU. This returns the equivalent of what in the stream
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+ * protocol is the outstanding interrupt sent with a Forward packet.
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+ */
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+GICv5PendingIrq gicv5_get_hppi(GICv5Common *cs, GICv5Domain domain,
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+ uint32_t iaffid);
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+
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#endif
target/arm/tcg/gicv5-cpuif.c
+61
@@ -51,6 +51,10 @@ FIELD(ICC_CR0, PID, 38, 1)
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FIELD(ICC_PCR, PRIORITY, 0, 5)
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+FIELD(ICC_HPPIR_EL1, ID, 0, 24)
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+FIELD(ICC_HPPIR_EL1, TYPE, 29, 3)
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+FIELD(ICC_HPPIR_EL1, HPPIV, 32, 1)
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+
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/*
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* We implement 24 bits of interrupt ID, the mandated 5 bits of priority,
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* and no legacy GICv3.3 vcpu interface (yet)
@@ -114,6 +118,51 @@ static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)
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return hap < 32 ? hap : PRIO_IDLE;
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}
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+static GICv5PendingIrq gic_hppi(CPUARMState *env, GICv5Domain domain)
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+{
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+ /*
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+ * Return the current highest priority pending interrupt for the
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+ * specified domain, if it has sufficient priority to preempt. The
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+ * intid field of the return value will be in the format of the
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+ * ICC_HPPIR register (and will be zero if and only if there is no
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+ * interrupt that can preempt).
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+ */
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+
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+ GICv5Common *gic = gicv5_get_gic(env);
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+ GICv5PendingIrq best, irs_hppi;
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+
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+ if (!(env->gicv5_cpuif.icc_cr0[domain] & R_ICC_CR0_EN_MASK)) {
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+ /* If cpuif is disabled there is no HPPI */
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+ return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };
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+ }
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+
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+ irs_hppi = gicv5_get_hppi(gic, domain, env->gicv5_iaffid);
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+
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+ /*
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+ * If the best PPI and the best interrupt from the IRS have the
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+ * same priority, it's IMPDEF which we pick (R_VVBPS). We choose
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+ * the PPI.
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+ */
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+ if (env->gicv5_cpuif.ppi_hppi[domain].prio <= irs_hppi.prio) {
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+ best = env->gicv5_cpuif.ppi_hppi[domain];
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+ } else {
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+ best = irs_hppi;
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+ }
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+
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+ /*
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+ * D_MSQKF: an interrupt has sufficient priority if its priority
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+ * is higher than the current running priority and equal to or
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+ * higher than the priority mask.
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+ */
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+ if (best.prio == PRIO_IDLE ||
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+ best.prio > env->gicv5_cpuif.icc_pcr[domain] ||
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+ best.prio >= gic_running_prio(env, domain)) {
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+ return (GICv5PendingIrq) { .intid = 0, .prio = PRIO_IDLE };
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+ }
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+ best.intid |= R_ICC_HPPIR_EL1_HPPIV_MASK;
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+ return best;
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+}
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+
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static void gic_recalc_ppi_hppi(CPUARMState *env)
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{
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/*
@@ -407,6 +456,13 @@ static void gic_icc_pcr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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}
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}
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+static uint64_t gic_icc_hppir_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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+{
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+ GICv5Domain domain = gicv5_logical_domain(env);
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+ GICv5PendingIrq hppi = gic_hppi(env, domain);
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+ return hppi.intid;
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+}
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+
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static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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/*
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* Barrier: wait until the effects of a cpuif system register
@@ -522,6 +578,11 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]),
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.resetvalue = PPI_HMR1_RESET,
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},
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+ { .name = "ICC_HPPIR_EL1", .state = ARM_CP_STATE_AA64,
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+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 3,
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+ .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,
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+ .readfn = gic_icc_hppir_el1_read,
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+ },
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{ .name = "ICC_PPI_ENABLER0_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 10, .opc2 = 6,
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.access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,