hw/intc/arm_gicv5: Implement gicv5_request_config()
Implement the gicv5_request_config() function, which corresponds to the RequestConfig command and its RequestConfigAck reply. We provide read_l2_iste() as a separate function to keep the "access the in-guest-memory data structure" layer separate from the "operate on the L2_ISTE values" layer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260327111700.795099-26-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
a05e5124068a36c72db85986b03da500facda40a
3 files changed
+127
hw/intc/arm_gicv5.c
+102
@@ -297,6 +297,19 @@ FIELD(L2_ISTE, HWU, 9, 2)
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FIELD(L2_ISTE, PRIORITY, 11, 5)
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FIELD(L2_ISTE, IAFFID, 16, 16)
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+/*
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+ * Format used for gicv5_request_config() return value, which matches
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+ * the ICC_ICSR_EL1 bit layout.
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+ */
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+FIELD(ICSR, F, 0, 1)
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+FIELD(ICSR, ENABLED, 1, 1)
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+FIELD(ICSR, PENDING, 2, 1)
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+FIELD(ICSR, IRM, 3, 1)
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+FIELD(ICSR, ACTIVE, 4, 1)
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+FIELD(ICSR, HM, 5, 1)
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+FIELD(ICSR, PRIORITY, 11, 5)
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+FIELD(ICSR, IAFFID, 32, 16)
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+
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static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain)
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{
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/*
@@ -713,6 +726,95 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,
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}
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}
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+static uint64_t l2_iste_to_icsr(GICv5Common *cs, const GICv5ISTConfig *cfg,
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+ uint32_t id)
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+{
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+ uint64_t icsr = 0;
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+ const uint32_t *l2_iste_p;
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+ L2_ISTE_Handle h;
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+
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+ l2_iste_p = get_l2_iste(cs, cfg, id, &h);
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+ if (!l2_iste_p) {
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+ return R_ICSR_F_MASK;
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+ }
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+
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+ /*
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+ * The field locations in the L2 ISTE do not line up with the
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+ * corresponding fields in the ICC_ICSR_EL1 register, so we need
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+ * to extract and deposit them individually.
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+ */
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+ icsr = FIELD_DP64(icsr, ICSR, F, 0);
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+ icsr = FIELD_DP64(icsr, ICSR, ENABLED, FIELD_EX32(*l2_iste_p, L2_ISTE, ENABLE));
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+ icsr = FIELD_DP64(icsr, ICSR, PENDING, FIELD_EX32(*l2_iste_p, L2_ISTE, PENDING));
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+ icsr = FIELD_DP64(icsr, ICSR, IRM, FIELD_EX32(*l2_iste_p, L2_ISTE, IRM));
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+ icsr = FIELD_DP64(icsr, ICSR, ACTIVE, FIELD_EX32(*l2_iste_p, L2_ISTE, ACTIVE));
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+ icsr = FIELD_DP64(icsr, ICSR, HM, FIELD_EX32(*l2_iste_p, L2_ISTE, HM));
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+ icsr = FIELD_DP64(icsr, ICSR, PRIORITY, FIELD_EX32(*l2_iste_p, L2_ISTE, PRIORITY));
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+ icsr = FIELD_DP64(icsr, ICSR, IAFFID, FIELD_EX32(*l2_iste_p, L2_ISTE, IAFFID));
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+
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+ return icsr;
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+}
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+
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+static uint64_t spi_state_to_icsr(GICv5SPIState *spi)
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+{
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+ uint64_t icsr = 0;
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+
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+ icsr = FIELD_DP64(icsr, ICSR, F, 0);
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+ icsr = FIELD_DP64(icsr, ICSR, ENABLED, spi->enabled);
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+ icsr = FIELD_DP64(icsr, ICSR, PENDING, spi->pending);
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+ icsr = FIELD_DP64(icsr, ICSR, IRM, spi->irm);
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+ icsr = FIELD_DP64(icsr, ICSR, ACTIVE, spi->active);
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+ icsr = FIELD_DP64(icsr, ICSR, HM, spi->hm);
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+ icsr = FIELD_DP64(icsr, ICSR, PRIORITY, spi->priority);
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+ icsr = FIELD_DP64(icsr, ICSR, IAFFID, spi->iaffid);
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+
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+ return icsr;
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+}
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+
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+uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,
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+ GICv5IntType type, bool virtual)
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+{
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+ GICv5 *s = ARM_GICV5(cs);
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+ uint64_t icsr;
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+
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+ if (virtual) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to "
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+ "read config of a virtual interrupt\n");
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+ return R_ICSR_F_MASK;
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+ }
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+
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+ switch (type) {
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+ case GICV5_LPI:
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+ {
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+ const GICv5ISTConfig *cfg = &s->phys_lpi_config[domain];
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+
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+ icsr = l2_iste_to_icsr(cs, cfg, id);
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+ trace_gicv5_request_config(domain_name[domain], inttype_name(type),
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+ virtual, id, icsr);
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+ return icsr;
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+ }
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+ case GICV5_SPI:
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+ {
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+ GICv5SPIState *spi = gicv5_spi_state(cs, id, domain);
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+
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+ if (!spi) {
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to "
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+ "read config of unreachable SPI %d\n", id);
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+ return R_ICSR_F_MASK;
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+ }
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+
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+ icsr = spi_state_to_icsr(spi);
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+ trace_gicv5_request_config(domain_name[domain], inttype_name(type),
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+ virtual, id, icsr);
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+ return icsr;
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+ }
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+ default:
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+ qemu_log_mask(LOG_GUEST_ERROR, "gicv5_request_config: tried to "
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+ "read config of bad interrupt type %d\n", type);
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+ return R_ICSR_F_MASK;
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+ }
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+}
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+
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static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)
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{
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GICv5Common *cs = ARM_GICV5_COMMON(s);
hw/intc/trace-events
+1
@@ -240,6 +240,7 @@ gicv5_set_enabled(const char *domain, const char *type, bool virtual, uint32_t i
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gicv5_set_pending(const char *domain, const char *type, bool virtual, uint32_t id, bool pending) "GICv5 IRS SetPending %s %s virtual:%d ID %u pending %d"
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gicv5_set_handling(const char *domain, const char *type, bool virtual, uint32_t id, int handling) "GICv5 IRS SetHandling %s %s virtual:%d ID %u handling %d"
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gicv5_set_target(const char *domain, const char *type, bool virtual, uint32_t id, uint32_t iaffid, int irm) "GICv5 IRS SetTarget %s %s virtual:%d ID %u IAFFID %u routingmode %d"
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+gicv5_request_config(const char *domain, const char *type, bool virtual, uint32_t id, uint64_t icsr) "GICv5 IRS RequestConfig %s %s virtual:%d ID %u ICSR 0x%" PRIx64
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# arm_gicv5_common.c
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gicv5_common_realize(uint32_t irsid, uint32_t num_cpus, uint32_t spi_base, uint32_t spi_irs_range, uint32_t spi_range) "GICv5 IRS realized: IRS ID %u, %u CPUs, SPI base %u, SPI IRS range %u, SPI range %u"
include/hw/intc/arm_gicv5_stream.h
+24
@@ -126,4 +126,28 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id,
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void gicv5_set_target(GICv5Common *cs, uint32_t id, uint32_t iaffid,
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GICv5RoutingMode irm, GICv5Domain domain,
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GICv5IntType type, bool virtual);
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+
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+/**
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+ * gicv5_request_config
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+ * @cs: GIC IRS to send command to
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+ * @id: interrupt ID
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+ * @domain: interrupt domain to act on
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+ * @type: interrupt type (LPI or SPI)
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+ * @virtual: true if this is a virtual interrupt
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+ *
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+ * Query the current configuration of an interrupt; matches stream
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+ * interface RequestConfig command from CPUIF to IRS and the
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+ * RequestConfigAck reply to it.
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+ *
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+ * In the real stream protocol, the RequestConfigAck packet has the
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+ * same information as the register but in a different order; we use
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+ * the register order, not the packet order, so we don't need to
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+ * unpack and repack in the cpuif.
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+ *
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+ * Returns: the config of the interrupt, in the format used by
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+ * ICC_ICSR_EL1.
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+ */
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+uint64_t gicv5_request_config(GICv5Common *cs, uint32_t id, GICv5Domain domain,
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+ GICv5IntType type, bool virtual);
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+
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#endif