hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA
The GICv5 IRS keeps data structures in system memory. (Notably, it stores per-interrupt configuration information like the interrupt priority and its active and pending state in an in-memory data structure.) Add a link property so that the board or SoC can wire up a MemoryRegion that we will do DMA to. We name this property "sysmem" to match the GICv3's equivalent property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260327111700.795099-12-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
a6af4dc6dda492e76978b4b8bd910cb5bc84ac7e
2 files changed
+12
hw/intc/arm_gicv5_common.c
+8
@@ -122,6 +122,12 @@ static void gicv5_common_realize(DeviceState *dev, Error **errp)
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cs->spi_base, cs->spi_irs_range, cs->spi_range);
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return;
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}
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+ if (!cs->dma) {
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+ error_setg(errp, "sysmem link property not set");
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+ return;
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+ }
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+
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+ address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem");
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trace_gicv5_common_realize(cs->irsid, cs->num_cpus,
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cs->spi_base, cs->spi_irs_range, cs->spi_range);
@@ -137,6 +143,8 @@ static const Property arm_gicv5_common_properties[] = {
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DEFINE_PROP_UINT32("spi-base", GICv5Common, spi_base, 0),
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DEFINE_PROP_UINT32("spi-irs-range", GICv5Common, spi_irs_range,
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GICV5_SPI_IRS_RANGE_NOT_SET),
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+ DEFINE_PROP_LINK("sysmem", GICv5Common, dma, TYPE_MEMORY_REGION,
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+ MemoryRegion *),
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};
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static void gicv5_common_class_init(ObjectClass *oc, const void *data)
include/hw/intc/arm_gicv5_common.h
+4
@@ -83,6 +83,10 @@ struct GICv5Common {
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uint32_t num_cpu_iaffids;
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uint32_t *cpu_iaffids;
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+ /* MemoryRegion and AS to DMA to/from for in-memory data structures */
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+ MemoryRegion *dma;
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+ AddressSpace dma_as;
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+
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uint32_t irsid;
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uint32_t spi_base;
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uint32_t spi_irs_range;