target/riscv: Add cfg properties for Zvfbfa extensions
The Zvfbfa extension adds more complete BF16 vector compute support and requires the Zve32f and Zfbfmin extensions. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20260402125234.1371897-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Max Chou committed
Apr 2, 2026 at 20:52 UTC
aa55c15bfa3e84782ebe8af10c3a8ba0e3d7a1a3
3 files changed
+10
target/riscv/cpu.c
+1
@@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
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ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
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ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
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+ ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),
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ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
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ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
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ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
target/riscv/cpu_cfg_fields.h.inc
+1
@@ -100,6 +100,7 @@ BOOL_FIELD(ext_zvks)
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BOOL_FIELD(ext_zvksc)
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BOOL_FIELD(ext_zvksg)
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BOOL_FIELD(ext_zmmul)
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+BOOL_FIELD(ext_zvfbfa)
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BOOL_FIELD(ext_zvfbfmin)
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BOOL_FIELD(ext_zvfbfwma)
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BOOL_FIELD(ext_zvfh)
target/riscv/tcg/tcg-cpu.c
+8
@@ -720,6 +720,14 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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return;
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}
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+ if (cpu->cfg.ext_zvfbfa) {
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+ if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) {
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+ error_setg(errp, "Zvfbfa extension requires Zve32f extension "
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+ "and Zfbfmin extension");
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+ return;
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+ }
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+ }
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+
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if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
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error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
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return;