target/or1k: Use XML register definitions from GDB
Import gdb-xml/or1k-fpu.xml from mainstream binutils, tag 'binutils-2_46' [*]. Register as CPUClass::gdb_core_xml_file. [*] https://sourceware.org/git/?p=binutils-gdb.git;a=blob_plain;f=gdb/features/or1k-core.xml;h=0d13f355f5296ae426794eb3003dcc18fbbd49d5;hb=refs/tags/binutils-2_46 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20260219191955.83815-23-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Feb 17, 2026 at 08:19 UTC
aa75a7c09b5a4f9e3478c65261ec80ab48720925
5 files changed
+69
-1
MAINTAINERS
+1
@@ -304,6 +304,7 @@ M: Stafford Horne <shorne@gmail.com>
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S: Odd Fixes
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F: docs/system/or1k/cpu-features.rst
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F: target/or1k/
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+F: gdb-xml/or1k-core.xml
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F: hw/or1k/
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F: include/hw/or1k/
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F: tests/functional/or1k/meson.build
configs/targets/or1k-linux-user.mak
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@@ -2,5 +2,6 @@ TARGET_ARCH=or1k
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TARGET_BIG_ENDIAN=y
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TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat
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TARGET_SYSTBL=syscall.tbl
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+TARGET_XML_FILES= gdb-xml/or1k-core.xml
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TARGET_LONG_BITS=32
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TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
configs/targets/or1k-softmmu.mak
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@@ -2,6 +2,7 @@ TARGET_ARCH=or1k
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TARGET_BIG_ENDIAN=y
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# needed by boot.c and all boards
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TARGET_NEED_FDT=y
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+TARGET_XML_FILES= gdb-xml/or1k-core.xml
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TARGET_LONG_BITS=32
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TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
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TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
gdb-xml/or1k-core.xml
new
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@@ -0,0 +1,65 @@
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+<?xml version="1.0"?>
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+<!-- Copyright (C) 2017-2026 Free Software Foundation, Inc.
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+
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+ Copying and distribution of this file, with or without modification,
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+ are permitted in any medium without royalty provided the copyright
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+ notice and this notice are preserved. -->
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+
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+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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+<feature name="org.gnu.gdb.or1k.group0">
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+ <reg name="r0" bitsize="32" type="int"/>
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+ <reg name="r1" bitsize="32" type="data_ptr"/>
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+ <reg name="r2" bitsize="32" type="data_ptr"/>
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+ <reg name="r3" bitsize="32" type="int"/>
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+ <reg name="r4" bitsize="32" type="int"/>
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+ <reg name="r5" bitsize="32" type="int"/>
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+ <reg name="r6" bitsize="32" type="int"/>
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+ <reg name="r7" bitsize="32" type="int"/>
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+ <reg name="r8" bitsize="32" type="int"/>
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+ <reg name="r9" bitsize="32" type="code_ptr"/>
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+ <reg name="r10" bitsize="32" type="int"/>
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+ <reg name="r11" bitsize="32" type="int"/>
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+ <reg name="r12" bitsize="32" type="int"/>
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+ <reg name="r13" bitsize="32" type="int"/>
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+ <reg name="r14" bitsize="32" type="int"/>
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+ <reg name="r15" bitsize="32" type="int"/>
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+ <reg name="r16" bitsize="32" type="int"/>
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+ <reg name="r17" bitsize="32" type="int"/>
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+ <reg name="r18" bitsize="32" type="int"/>
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+ <reg name="r19" bitsize="32" type="int"/>
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+ <reg name="r20" bitsize="32" type="int"/>
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+ <reg name="r21" bitsize="32" type="int"/>
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+ <reg name="r22" bitsize="32" type="int"/>
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+ <reg name="r23" bitsize="32" type="int"/>
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+ <reg name="r24" bitsize="32" type="int"/>
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+ <reg name="r25" bitsize="32" type="int"/>
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+ <reg name="r26" bitsize="32" type="int"/>
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+ <reg name="r27" bitsize="32" type="int"/>
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+ <reg name="r28" bitsize="32" type="int"/>
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+ <reg name="r29" bitsize="32" type="int"/>
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+ <reg name="r30" bitsize="32" type="int"/>
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+ <reg name="r31" bitsize="32" type="int"/>
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+ <reg name="ppc" bitsize="32" type="code_ptr"/>
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+ <reg name="npc" bitsize="32" type="code_ptr"/>
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+ <flags id="sr_flags" size="4">
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+ <field name="SM" start="0" end="0"/>
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+ <field name="TEE" start="1" end="1"/>
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+ <field name="IEE" start="2" end="2"/>
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+ <field name="DCE" start="3" end="3"/>
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+ <field name="ICE" start="4" end="4"/>
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+ <field name="DME" start="5" end="5"/>
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+ <field name="IME" start="6" end="6"/>
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+ <field name="LEE" start="7" end="7"/>
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+ <field name="CE" start="8" end="8"/>
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+ <field name="F" start="9" end="9"/>
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+ <field name="CY" start="10" end="10"/>
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+ <field name="OV" start="11" end="11"/>
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+ <field name="OVE" start="12" end="12"/>
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+ <field name="DSX" start="13" end="13"/>
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+ <field name="EPH" start="14" end="14"/>
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+ <field name="FO" start="15" end="15"/>
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+ <field name="SUMRA" start="16" end="16"/>
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+ <field name="CID" start="28" end="31"/>
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+ </flags>
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+ <reg name="sr" bitsize="32" type="sr_flags"/>
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+</feature>
target/or1k/cpu.c
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-1
@@ -288,13 +288,13 @@ static void openrisc_cpu_class_init(ObjectClass *oc, const void *data)
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cc->dump_state = openrisc_cpu_dump_state;
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cc->set_pc = openrisc_cpu_set_pc;
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cc->get_pc = openrisc_cpu_get_pc;
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+ cc->gdb_core_xml_file = "or1k-core.xml";
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cc->gdb_read_register = openrisc_cpu_gdb_read_register;
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cc->gdb_write_register = openrisc_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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dc->vmsd = &vmstate_openrisc_cpu;
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cc->sysemu_ops = &openrisc_sysemu_ops;
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#endif
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- cc->gdb_num_core_regs = 32 + 3;
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cc->disas_set_info = openrisc_disas_set_info;
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cc->tcg_ops = &openrisc_tcg_ops;
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}