target/arm: migrate debug syndromes to registerfields
Migrate syn_swstep, syn_watchpoint and syn_breakpoint to the registerfields API. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-12-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
ab62f2f10c6507f6f5ea2af175317b7fc555b931
1 file changed
+48
-6
target/arm/syndrome.h
+48
-6
@@ -595,22 +595,64 @@ static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc)
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return res;
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}
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+/*
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+ * ISS encoding for an exception from a Software Step exception.
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+ */
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+FIELD(SOFTSTEP_ISS, IFSC, 0, 6)
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+FIELD(SOFTSTEP_ISS, EX, 6, 1)
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+FIELD(SOFTSTEP_ISS, ISV, 24, 1)
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+
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static inline uint32_t syn_swstep(int same_el, int isv, int ex)
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{
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- return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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- | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
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+ uint32_t res = syn_set_ec(0, EC_SOFTWARESTEP + same_el);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, SOFTSTEP_ISS, ISV, isv);
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+ res = FIELD_DP32(res, SOFTSTEP_ISS, EX, ex);
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+ res = FIELD_DP32(res, SOFTSTEP_ISS, IFSC, 0x22);
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+
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+ return res;
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}
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+/*
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+ * ISS encoding for an exception from a Watchpoint exception
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+ */
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+FIELD(WATCHPOINT_ISS, DFSC, 0, 6)
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+FIELD(WATCHPOINT_ISS, WNR, 6, 1)
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+FIELD(WATCHPOINT_ISS, CM, 8, 1)
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+FIELD(WATCHPOINT_ISS, FnV, 10, 1)
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+FIELD(WATCHPOINT_ISS, VNCR, 13, 1) /* FEAT_NV2 */
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+FIELD(WATCHPOINT_ISS, FnP, 15, 1)
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+FIELD(WATCHPOINT_ISS, WPF, 16, 1)
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+/* bellow mandatory from FEAT_Debugv8p9 */
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+FIELD(WATCHPOINT_ISS, WPTV, 17, 1) /* FEAT_Debugv8p2 - WPT valid */
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+FIELD(WATCHPOINT_ISS, WPT, 18, 6) /* FEAT_Debugv8p2 - missing WP number */
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+
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static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
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{
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- return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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- | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
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+ uint32_t res = syn_set_ec(0, EC_WATCHPOINT + same_el);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, WATCHPOINT_ISS, CM, cm);
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+ res = FIELD_DP32(res, WATCHPOINT_ISS, WNR, wnr);
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+ res = FIELD_DP32(res, WATCHPOINT_ISS, DFSC, 0x22);
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+
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+ return res;
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}
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+/*
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+ * ISS encoding for an exception from a Breakpoint or a Vector Catch
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+ * debug exception.
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+ */
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+FIELD(BREAKPOINT_ISS, IFSC, 0, 6)
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+
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static inline uint32_t syn_breakpoint(int same_el)
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{
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- return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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- | ARM_EL_IL | 0x22;
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+ uint32_t res = syn_set_ec(0, EC_BREAKPOINT + same_el);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+ res = FIELD_DP32(res, BREAKPOINT_ISS, IFSC, 0x22);
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+
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+ return res;
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}
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static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)