disas: diassemble RISC-V xlrbr (crc32) instructions
Placed in a separate file as a vendor extension. Signed-off-by: James Wainwright <james.wainwright@lowrisc.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260320134254.217123-4-james.wainwright@lowrisc.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Emmanuel Blot committed
Mar 20, 2026 at 13:42 UTC
af58a69046e951b351155718dac2a1b0798a71a2
5 files changed
+103
-2
MAINTAINERS
+1
-1
@@ -4135,7 +4135,7 @@ R: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
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L: qemu-riscv@nongnu.org
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S: Maintained
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F: tcg/riscv64/
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-F: disas/riscv.[ch]
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+F: disas/riscv*.[ch]
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S390 TCG target
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M: Richard Henderson <richard.henderson@linaro.org>
disas/meson.build
+2
-1
@@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))
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common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
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'riscv.c',
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'riscv-xthead.c',
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- 'riscv-xventana.c'
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+ 'riscv-xventana.c',
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+ 'riscv-xlrbr.c'
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))
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common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
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common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
disas/riscv-xlrbr.c
new
+79
@@ -0,0 +1,79 @@
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+/*
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+ * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
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+ * bitmanip extension v0.93.
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+ *
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+ * Copyright (c) 2023 Rivos Inc
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include "qemu/osdep.h"
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+
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+#include "disas/riscv.h"
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+#include "disas/riscv-xlrbr.h"
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+
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+typedef enum {
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+ /* 0 is reserved for rv_op_illegal. */
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+ rv_op_crc32_b = 1,
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+ rv_op_crc32_h = 2,
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+ rv_op_crc32_w = 3,
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+ rv_op_crc32_d = 4,
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+ rv_op_crc32c_b = 5,
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+ rv_op_crc32c_h = 6,
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+ rv_op_crc32c_w = 7,
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+ rv_op_crc32c_d = 8,
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+} rv_xlrbr_op;
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+
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+const rv_opcode_data rv_xlrbr_opcode_data[] = {
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+ { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
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+ { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+};
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+
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+void decode_xlrbr(rv_decode *dec, rv_isa isa)
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+{
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+ rv_inst inst = dec->inst;
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+ rv_opcode op = rv_op_illegal;
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+
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+ switch ((inst >> 0) & 0b1111111) {
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+ case 0b0010011:
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+ switch ((inst >> 12) & 0b111) {
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+ case 0b001:
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+ switch ((inst >> 20 & 0b111111111111)) {
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+ case 0b011000010000:
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+ op = rv_op_crc32_b;
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+ break;
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+ case 0b011000010001:
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+ op = rv_op_crc32_h;
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+ break;
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+ case 0b011000010010:
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+ op = rv_op_crc32_w;
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+ break;
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+ case 0b011000010011:
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+ op = rv_op_crc32_d;
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+ break;
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+ case 0b011000011000:
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+ op = rv_op_crc32c_b;
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+ break;
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+ case 0b011000011001:
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+ op = rv_op_crc32c_h;
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+ break;
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+ case 0b011000011010:
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+ op = rv_op_crc32c_w;
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+ break;
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+ case 0b011000011011:
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+ op = rv_op_crc32c_d;
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+ break;
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+ }
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+ break;
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+ }
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+ break;
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+ }
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+ dec->op = op;
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+}
disas/riscv-xlrbr.h
new
+19
@@ -0,0 +1,19 @@
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+/*
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+ * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32
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+ * bitmanip extension v0.93.
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+ *
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+ * Copyright (c) 2023 Rivos Inc
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#ifndef DISAS_RISCV_XLRBR_H
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+#define DISAS_RISCV_XLRBR_H
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+
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+#include "disas/riscv.h"
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+
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+extern const rv_opcode_data rv_xlrbr_opcode_data[];
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+
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+void decode_xlrbr(rv_decode *, rv_isa);
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+
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+#endif /* DISAS_RISCV_XLRBR_H */
disas/riscv.c
+2
@@ -26,6 +26,7 @@
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/* Vendor extensions */
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#include "disas/riscv-xthead.h"
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#include "disas/riscv-xventana.h"
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+#include "disas/riscv-xlrbr.h"
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typedef enum {
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/* 0 is reserved for rv_op_illegal. */
@@ -5434,6 +5435,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
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{ has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
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{ has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
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{ has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
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+ { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },
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};
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for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {