@samitouri / QOSamiQemu / commits / b4e2f59e71

target/mips: Expand TCGv type for 64-bit extensions

These TX79, Octeon and Loongarch extensions are only built as 64-bit, so TCGv expands to TCGv_i64. Use the latter which is more explicit. Mechanical changes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20260401144503.80510-3-philmd@linaro.org>

Philippe Mathieu-Daudé committed Apr 1, 2026 at 16:26 UTC b4e2f59e7144ed5e5799c6c351d4013650aab8c3
4 files changed +91 -91
target/mips/tcg/lcsr_translate.c
+8 -8
@@ -18,8 +18,8 @@
18
19 static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)
20 {
21 - TCGv dest = tcg_temp_new();
22 - TCGv src1 = tcg_temp_new();
21 + TCGv_i64 dest = tcg_temp_new_i64();
22 + TCGv_i64 src1 = tcg_temp_new_i64();
23
24 gen_load_gpr(src1, a->rs);
25 gen_helper_lcsr_cpucfg(dest, tcg_env, src1);
@@ -30,10 +30,10 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)
30
31 #ifndef CONFIG_USER_ONLY
32 static bool gen_rdcsr(DisasContext *ctx, arg_r *a,
33 - void (*func)(TCGv, TCGv_ptr, TCGv))
33 + void (*func)(TCGv_i64, TCGv_ptr, TCGv_i64))
34 {
35 - TCGv dest = tcg_temp_new();
36 - TCGv src1 = tcg_temp_new();
35 + TCGv_i64 dest = tcg_temp_new_i64();
36 + TCGv_i64 src1 = tcg_temp_new_i64();
37
38 check_cp0_enabled(ctx);
39 gen_load_gpr(src1, a->rs);
@@ -44,10 +44,10 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a,
44 }
45
46 static bool gen_wrcsr(DisasContext *ctx, arg_r *a,
47 - void (*func)(TCGv_ptr, TCGv, TCGv))
47 + void (*func)(TCGv_ptr, TCGv_i64, TCGv_i64))
48 {
49 - TCGv val = tcg_temp_new();
50 - TCGv addr = tcg_temp_new();
49 + TCGv_i64 val = tcg_temp_new_i64();
50 + TCGv_i64 addr = tcg_temp_new_i64();
51
52 check_cp0_enabled(ctx);
53 gen_load_gpr(addr, a->rs);
target/mips/tcg/loong_translate.c
+46 -46
@@ -28,7 +28,7 @@
28 static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
29 bool is_double)
30 {
31 - TCGv t0, t1;
31 + TCGv_i64 t0, t1;
32 TCGLabel *l1, *l2, *l3;
33
34 if (rd == 0) {
@@ -36,8 +36,8 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
36 return true;
37 }
38
39 - t0 = tcg_temp_new();
40 - t1 = tcg_temp_new();
39 + t0 = tcg_temp_new_i64();
40 + t1 = tcg_temp_new_i64();
41 l1 = gen_new_label();
42 l2 = gen_new_label();
43 l3 = gen_new_label();
@@ -46,23 +46,23 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
46 gen_load_gpr(t1, rt);
47
48 if (!is_double) {
49 - tcg_gen_ext32s_tl(t0, t0);
50 - tcg_gen_ext32s_tl(t1, t1);
49 + tcg_gen_ext32s_i64(t0, t0);
50 + tcg_gen_ext32s_i64(t1, t1);
51 }
52 - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
53 - tcg_gen_movi_tl(cpu_gpr[rd], 0);
52 + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);
53 + tcg_gen_movi_i64(cpu_gpr[rd], 0);
54 tcg_gen_br(l3);
55 gen_set_label(l1);
56
57 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
58 - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
59 - tcg_gen_mov_tl(cpu_gpr[rd], t0);
57 + tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
58 + tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2);
59 + tcg_gen_mov_i64(cpu_gpr[rd], t0);
60
61 tcg_gen_br(l3);
62 gen_set_label(l2);
63 - tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
63 + tcg_gen_div_i64(cpu_gpr[rd], t0, t1);
64 if (!is_double) {
65 - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
65 + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);
66 }
67 gen_set_label(l3);
68
@@ -82,7 +82,7 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
82 static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
83 bool is_double)
84 {
85 - TCGv t0, t1;
85 + TCGv_i64 t0, t1;
86 TCGLabel *l1, *l2;
87
88 if (rd == 0) {
@@ -90,8 +90,8 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
90 return true;
91 }
92
93 - t0 = tcg_temp_new();
94 - t1 = tcg_temp_new();
93 + t0 = tcg_temp_new_i64();
94 + t1 = tcg_temp_new_i64();
95 l1 = gen_new_label();
96 l2 = gen_new_label();
97
@@ -99,17 +99,17 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
99 gen_load_gpr(t1, rt);
100
101 if (!is_double) {
102 - tcg_gen_ext32u_tl(t0, t0);
103 - tcg_gen_ext32u_tl(t1, t1);
102 + tcg_gen_ext32u_i64(t0, t0);
103 + tcg_gen_ext32u_i64(t1, t1);
104 }
105 - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
106 - tcg_gen_movi_tl(cpu_gpr[rd], 0);
105 + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);
106 + tcg_gen_movi_i64(cpu_gpr[rd], 0);
107
108 tcg_gen_br(l2);
109 gen_set_label(l1);
110 - tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
110 + tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
111 if (!is_double) {
112 - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
112 + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);
113 }
114 gen_set_label(l2);
115
@@ -129,7 +129,7 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
129 static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
130 bool is_double)
131 {
132 - TCGv t0, t1;
132 + TCGv_i64 t0, t1;
133 TCGLabel *l1, *l2, *l3;
134
135 if (rd == 0) {
@@ -137,8 +137,8 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
137 return true;
138 }
139
140 - t0 = tcg_temp_new();
141 - t1 = tcg_temp_new();
140 + t0 = tcg_temp_new_i64();
141 + t1 = tcg_temp_new_i64();
142 l1 = gen_new_label();
143 l2 = gen_new_label();
144 l3 = gen_new_label();
@@ -147,19 +147,19 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
147 gen_load_gpr(t1, rt);
148
149 if (!is_double) {
150 - tcg_gen_ext32u_tl(t0, t0);
151 - tcg_gen_ext32u_tl(t1, t1);
150 + tcg_gen_ext32u_i64(t0, t0);
151 + tcg_gen_ext32u_i64(t1, t1);
152 }
153 - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
154 - tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
155 - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
153 + tcg_gen_brcondi_i64(TCG_COND_EQ, t1, 0, l1);
154 + tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
155 + tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2);
156 gen_set_label(l1);
157 - tcg_gen_movi_tl(cpu_gpr[rd], 0);
157 + tcg_gen_movi_i64(cpu_gpr[rd], 0);
158 tcg_gen_br(l3);
159 gen_set_label(l2);
160 - tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
160 + tcg_gen_rem_i64(cpu_gpr[rd], t0, t1);
161 if (!is_double) {
162 - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
162 + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);
163 }
164 gen_set_label(l3);
165
@@ -179,7 +179,7 @@ static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)
179 static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
180 bool is_double)
181 {
182 - TCGv t0, t1;
182 + TCGv_i64 t0, t1;
183 TCGLabel *l1, *l2;
184
185 if (rd == 0) {
@@ -187,8 +187,8 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
187 return true;
188 }
189
190 - t0 = tcg_temp_new();
191 - t1 = tcg_temp_new();
190 + t0 = tcg_temp_new_i64();
191 + t1 = tcg_temp_new_i64();
192 l1 = gen_new_label();
193 l2 = gen_new_label();
194
@@ -196,16 +196,16 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
196 gen_load_gpr(t1, rt);
197
198 if (!is_double) {
199 - tcg_gen_ext32u_tl(t0, t0);
200 - tcg_gen_ext32u_tl(t1, t1);
199 + tcg_gen_ext32u_i64(t0, t0);
200 + tcg_gen_ext32u_i64(t1, t1);
201 }
202 - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
203 - tcg_gen_movi_tl(cpu_gpr[rd], 0);
202 + tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);
203 + tcg_gen_movi_i64(cpu_gpr[rd], 0);
204 tcg_gen_br(l2);
205 gen_set_label(l1);
206 - tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
206 + tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
207 if (!is_double) {
208 - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
208 + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);
209 }
210 gen_set_label(l2);
211
@@ -225,22 +225,22 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
225 static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
226 bool is_double)
227 {
228 - TCGv t0, t1;
228 + TCGv_i64 t0, t1;
229
230 if (rd == 0) {
231 /* Treat as NOP. */
232 return true;
233 }
234
235 - t0 = tcg_temp_new();
236 - t1 = tcg_temp_new();
235 + t0 = tcg_temp_new_i64();
236 + t1 = tcg_temp_new_i64();
237
238 gen_load_gpr(t0, rs);
239 gen_load_gpr(t1, rt);
240
241 - tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
241 + tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
242 if (!is_double) {
243 - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
243 + tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);
244 }
245
246 return true;
target/mips/tcg/octeon_translate.c
+30 -30
@@ -15,7 +15,7 @@
15
16 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
17 {
18 - TCGv p;
18 + TCGv_i64 p;
19
20 if (ctx->hflags & MIPS_HFLAG_BMASK) {
21 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n",
@@ -25,14 +25,14 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
25 }
26
27 /* Load needed operands */
28 - TCGv t0 = tcg_temp_new();
28 + TCGv_i64 t0 = tcg_temp_new_i64();
29 gen_load_gpr(t0, a->rs);
30
31 - p = tcg_constant_tl(1ULL << a->p);
31 + p = tcg_constant_i64(1ULL << a->p);
32 if (a->set) {
33 - tcg_gen_and_tl(bcond, p, t0);
33 + tcg_gen_and_i64(bcond, p, t0);
34 } else {
35 - tcg_gen_andc_tl(bcond, p, t0);
35 + tcg_gen_andc_i64(bcond, p, t0);
36 }
37
38 ctx->hflags |= MIPS_HFLAG_BC;
@@ -43,34 +43,34 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
43
44 static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
45 {
46 - TCGv t0, t1;
46 + TCGv_i64 t0, t1;
47
48 if (a->rt == 0) {
49 /* nop */
50 return true;
51 }
52
53 - t0 = tcg_temp_new();
54 - t1 = tcg_temp_new();
53 + t0 = tcg_temp_new_i64();
54 + t1 = tcg_temp_new_i64();
55 gen_load_gpr(t0, a->rs);
56 gen_load_gpr(t1, a->rt);
57
58 - tcg_gen_add_tl(t0, t0, t1);
58 + tcg_gen_add_i64(t0, t0, t1);
59 tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
60 return true;
61 }
62
63 static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
64 {
65 - TCGv t0, t1;
65 + TCGv_i64 t0, t1;
66
67 if (a->rt == 0) {
68 /* nop */
69 return true;
70 }
71
72 - t0 = tcg_temp_new();
73 - t1 = tcg_temp_new();
72 + t0 = tcg_temp_new_i64();
73 + t1 = tcg_temp_new_i64();
74 gen_load_gpr(t0, a->rs);
75 gen_load_gpr(t1, a->rt);
76
@@ -80,97 +80,97 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
80
81 static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
82 {
83 - TCGv t0;
83 + TCGv_i64 t0;
84
85 if (a->rt == 0) {
86 /* nop */
87 return true;
88 }
89
90 - t0 = tcg_temp_new();
90 + t0 = tcg_temp_new_i64();
91 gen_load_gpr(t0, a->rs);
92 - tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
92 + tcg_gen_sextract_i64(t0, t0, a->p, a->lenm1 + 1);
93 gen_store_gpr(t0, a->rt);
94 return true;
95 }
96
97 static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
98 {
99 - TCGv t0;
99 + TCGv_i64 t0;
100
101 if (a->rt == 0) {
102 /* nop */
103 return true;
104 }
105
106 - t0 = tcg_temp_new();
106 + t0 = tcg_temp_new_i64();
107 gen_load_gpr(t0, a->rs);
108 - tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
108 + tcg_gen_deposit_z_i64(t0, t0, a->p, a->lenm1 + 1);
109 gen_store_gpr(t0, a->rt);
110 return true;
111 }
112
113 static bool trans_POP(DisasContext *ctx, arg_POP *a)
114 {
115 - TCGv t0;
115 + TCGv_i64 t0;
116
117 if (a->rd == 0) {
118 /* nop */
119 return true;
120 }
121
122 - t0 = tcg_temp_new();
122 + t0 = tcg_temp_new_i64();
123 gen_load_gpr(t0, a->rs);
124 if (!a->dw) {
125 tcg_gen_andi_i64(t0, t0, 0xffffffff);
126 }
127 - tcg_gen_ctpop_tl(t0, t0);
127 + tcg_gen_ctpop_i64(t0, t0);
128 gen_store_gpr(t0, a->rd);
129 return true;
130 }
131
132 static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
133 {
134 - TCGv t0, t1;
134 + TCGv_i64 t0, t1;
135
136 if (a->rd == 0) {
137 /* nop */
138 return true;
139 }
140
141 - t0 = tcg_temp_new();
142 - t1 = tcg_temp_new();
141 + t0 = tcg_temp_new_i64();
142 + t1 = tcg_temp_new_i64();
143
144 gen_load_gpr(t0, a->rs);
145 gen_load_gpr(t1, a->rt);
146
147 if (a->ne) {
148 - tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
148 + tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
149 } else {
150 - tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
150 + tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
151 }
152 return true;
153 }
154
155 static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
156 {
157 - TCGv t0;
157 + TCGv_i64 t0;
158
159 if (a->rt == 0) {
160 /* nop */
161 return true;
162 }
163
164 - t0 = tcg_temp_new();
164 + t0 = tcg_temp_new_i64();
165
166 gen_load_gpr(t0, a->rs);
167
168 /* Sign-extend to 64 bit value */
169 target_ulong imm = a->imm;
170 if (a->ne) {
171 - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
171 + tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
172 } else {
173 - tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
173 + tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
174 }
175 return true;
176 }
target/mips/tcg/tx79_translate.c
+7 -7
@@ -241,8 +241,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
241 return true;
242 }
243
244 - c0 = tcg_constant_tl(0);
245 - c1 = tcg_constant_tl(0xffffffff);
244 + c0 = tcg_constant_i64(0);
245 + c1 = tcg_constant_i64(0xffffffff);
246 ax = tcg_temp_new_i64();
247 bx = tcg_temp_new_i64();
248 t0 = tcg_temp_new_i64();
@@ -322,7 +322,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_r *a)
322 static bool trans_LQ(DisasContext *ctx, arg_i *a)
323 {
324 TCGv_i64 t0;
325 - TCGv addr;
325 + TCGv_i64 addr;
326
327 if (a->rt == 0) {
328 /* nop */
@@ -330,14 +330,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
330 }
331
332 t0 = tcg_temp_new_i64();
333 - addr = tcg_temp_new();
333 + addr = tcg_temp_new_i64();
334
335 gen_base_offset_addr(ctx, addr, a->base, a->offset);
336 /*
337 * Clear least-significant four bits of the effective
338 * address, effectively creating an aligned address.
339 */
340 - tcg_gen_andi_tl(addr, addr, ~0xf);
340 + tcg_gen_andi_i64(addr, addr, ~0xf);
341
342 /* Lower half */
343 tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
@@ -353,14 +353,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
353 static bool trans_SQ(DisasContext *ctx, arg_i *a)
354 {
355 TCGv_i64 t0 = tcg_temp_new_i64();
356 - TCGv addr = tcg_temp_new();
356 + TCGv_i64 addr = tcg_temp_new_i64();
357
358 gen_base_offset_addr(ctx, addr, a->base, a->offset);
359 /*
360 * Clear least-significant four bits of the effective
361 * address, effectively creating an aligned address.
362 */
363 - tcg_gen_andi_tl(addr, addr, ~0xf);
363 + tcg_gen_andi_i64(addr, addr, ~0xf);
364
365 /* Lower half */
366 gen_load_gpr(t0, a->rt);