ppc/pnv: Add a nest MMU model
The nest MMU is used for translations needed by I/O subsystems on Power10. The nest is the shared, on-chip infrastructure that connects CPU cores, memory controllers, and I/O. This patch sets up a basic skeleton with its xscom area, mapping both needed xscom regions. Support required for PowerVM bringup. Use Power9 property for device tree to allow OPAL to work with Power9 and Power10. Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260120150139.714805-1-calebs@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Caleb Schlossin committed
Jan 20, 2026 at 09:01 UTC
b7d23294696e2da7006a63c1c7842ee8d469a82f
6 files changed
+188
hw/ppc/meson.build
+1
@@ -57,6 +57,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
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'pnv_nest_pervasive.c',
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'pnv_n1_chiplet.c',
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'pnv_mpipl.c',
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+ 'pnv_nmmu.c'
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))
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# PowerPC 4xx boards
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ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
hw/ppc/pnv.c
+20
@@ -2297,6 +2297,11 @@ static void pnv_chip_power10_instance_init(Object *obj)
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TYPE_PNV_PHB5_PEC);
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}
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+ for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {
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+ object_initialize_child(obj, "nmmu[*]", &chip10->nmmu[i],
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+ TYPE_PNV_NMMU);
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+ }
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+
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for (i = 0; i < pcc->i2c_num_engines; i++) {
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object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C);
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}
@@ -2511,6 +2516,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,
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&chip10->n1_chiplet.xscom_pb_es_mr);
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+ /* nest0/1 MMU */
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+ for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {
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+ object_property_set_int(OBJECT(&chip10->nmmu[i]), "nmmu_id",
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+ i , &error_fatal);
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+ object_property_set_link(OBJECT(&chip10->nmmu[i]), "chip",
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+ OBJECT(chip), &error_abort);
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+ if (!qdev_realize(DEVICE(&chip10->nmmu[i]), NULL, errp)) {
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+ return;
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+ }
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+ }
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+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST0_MMU_BASE,
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+ &chip10->nmmu[0].xscom_regs);
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+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_MMU_BASE,
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+ &chip10->nmmu[1].xscom_regs);
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+
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/* PHBs */
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pnv_chip_power10_phb_realize(chip, &local_err);
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if (local_err) {
hw/ppc/pnv_nmmu.c
new
+132
@@ -0,0 +1,132 @@
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+/*
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+ * QEMU PowerPC nest MMU model
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+ *
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+ * Copyright (c) 2025, IBM Corporation.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ *
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+ * This code is licensed under the GPL version 2 or later. See the
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+ * COPYING file in the top-level directory.
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+ */
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+
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+#include "qemu/osdep.h"
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+#include "qemu/log.h"
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+#include "hw/core/qdev-properties.h"
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+
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+#include "hw/ppc/pnv.h"
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+#include "hw/ppc/pnv_xscom.h"
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+#include "hw/ppc/pnv_nmmu.h"
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+#include "hw/ppc/fdt.h"
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+
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+#include <libfdt.h>
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+
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+#define NMMU_XLAT_CTL_PTCR 0xb
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+
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+static uint64_t pnv_nmmu_xscom_read(void *opaque, hwaddr addr, unsigned size)
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+{
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+ PnvNMMU *nmmu = PNV_NMMU(opaque);
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+ int reg = addr >> 3;
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+ uint64_t val;
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+
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+ if (reg == NMMU_XLAT_CTL_PTCR) {
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+ val = nmmu->ptcr;
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+ } else {
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+ val = 0xffffffffffffffffull;
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+ qemu_log_mask(LOG_UNIMP, "nMMU: xscom read at 0x%" PRIx32 "\n", reg);
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+ }
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+ return val;
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+}
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+
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+static void pnv_nmmu_xscom_write(void *opaque, hwaddr addr,
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+ uint64_t val, unsigned size)
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+{
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+ PnvNMMU *nmmu = PNV_NMMU(opaque);
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+ int reg = addr >> 3;
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+
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+ if (reg == NMMU_XLAT_CTL_PTCR) {
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+ nmmu->ptcr = val;
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+ } else {
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+ qemu_log_mask(LOG_UNIMP, "nMMU: xscom write at 0x%" PRIx32 "\n", reg);
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+ }
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+}
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+
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+static const MemoryRegionOps pnv_nmmu_xscom_ops = {
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+ .read = pnv_nmmu_xscom_read,
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+ .write = pnv_nmmu_xscom_write,
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+ .valid.min_access_size = 8,
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+ .valid.max_access_size = 8,
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+ .impl.min_access_size = 8,
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+ .impl.max_access_size = 8,
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+ .endianness = DEVICE_BIG_ENDIAN,
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+};
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+
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+static void pnv_nmmu_realize(DeviceState *dev, Error **errp)
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+{
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+ PnvNMMU *nmmu = PNV_NMMU(dev);
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+
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+ assert(nmmu->chip);
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+
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+ /* NMMU xscom region */
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+ pnv_xscom_region_init(&nmmu->xscom_regs, OBJECT(nmmu),
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+ &pnv_nmmu_xscom_ops, nmmu,
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+ "xscom-nmmu",
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+ PNV10_XSCOM_NMMU_SIZE);
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+}
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+
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+static int pnv_nmmu_dt_xscom(PnvXScomInterface *dev, void *fdt,
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+ int offset)
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+{
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+ PnvNMMU *nmmu = PNV_NMMU(dev);
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+ char *name;
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+ int nmmu_offset;
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+ const char compat[] = "ibm,power9-nest-mmu";
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+ uint32_t nmmu_pcba = PNV10_XSCOM_NEST0_MMU_BASE + nmmu->nmmu_id * 0x1000000;
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+ uint32_t reg[2] = {
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+ cpu_to_be32(nmmu_pcba),
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+ cpu_to_be32(PNV10_XSCOM_NMMU_SIZE)
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+ };
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+
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+ name = g_strdup_printf("nmmu@%x", nmmu_pcba);
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+ nmmu_offset = fdt_add_subnode(fdt, offset, name);
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+ _FDT(nmmu_offset);
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+ g_free(name);
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+
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+ _FDT(fdt_setprop(fdt, nmmu_offset, "reg", reg, sizeof(reg)));
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+ _FDT(fdt_setprop(fdt, nmmu_offset, "compatible", compat, sizeof(compat)));
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+ return 0;
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+}
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+
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+static const Property pnv_nmmu_properties[] = {
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+ DEFINE_PROP_UINT32("nmmu_id", PnvNMMU, nmmu_id, 0),
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+ DEFINE_PROP_LINK("chip", PnvNMMU, chip, TYPE_PNV_CHIP, PnvChip *),
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+};
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+
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+static void pnv_nmmu_class_init(ObjectClass *klass, const void *data)
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+{
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+ DeviceClass *dc = DEVICE_CLASS(klass);
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+ PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass);
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+
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+ xscomc->dt_xscom = pnv_nmmu_dt_xscom;
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+
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+ dc->desc = "PowerNV nest MMU";
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+ dc->realize = pnv_nmmu_realize;
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+ device_class_set_props(dc, pnv_nmmu_properties);
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+}
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+
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+static const TypeInfo pnv_nmmu_info = {
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+ .name = TYPE_PNV_NMMU,
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+ .parent = TYPE_DEVICE,
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+ .instance_size = sizeof(PnvNMMU),
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+ .class_init = pnv_nmmu_class_init,
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+ .interfaces = (InterfaceInfo[]) {
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+ { TYPE_PNV_XSCOM_INTERFACE },
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+ { }
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+ }
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+};
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+
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+static void pnv_nmmu_register_types(void)
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+{
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+ type_register_static(&pnv_nmmu_info);
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+}
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+
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+type_init(pnv_nmmu_register_types);
include/hw/ppc/pnv_chip.h
+3
@@ -7,6 +7,7 @@
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#include "hw/ppc/pnv_core.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_n1_chiplet.h"
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+#include "hw/ppc/pnv_nmmu.h"
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#include "hw/ssi/pnv_spi.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_occ.h"
@@ -126,6 +127,8 @@ struct Pnv10Chip {
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PnvN1Chiplet n1_chiplet;
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#define PNV10_CHIP_MAX_PIB_SPIC 6
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PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
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+#define PNV10_CHIP_MAX_NMMU 2
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+ PnvNMMU nmmu[PNV10_CHIP_MAX_NMMU];
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uint32_t nr_quads;
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PnvQuad *quads;
include/hw/ppc/pnv_nmmu.h
new
+28
@@ -0,0 +1,28 @@
1
+/*
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+ * QEMU PowerPC nest MMU model
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+ *
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+ * Copyright (c) 2025, IBM Corporation.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ *
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+ * This code is licensed under the GPL version 2 or later. See the
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+ * COPYING file in the top-level directory.
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+ */
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+
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+#ifndef PPC_PNV_NMMU_H
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+#define PPC_PNV_NMMU_H
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+
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+#define TYPE_PNV_NMMU "pnv-nmmu"
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+#define PNV_NMMU(obj) OBJECT_CHECK(PnvNMMU, (obj), TYPE_PNV_NMMU)
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+
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+typedef struct PnvNMMU {
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+ DeviceState parent;
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+
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+ struct PnvChip *chip;
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+
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+ MemoryRegion xscom_regs;
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+ uint32_t nmmu_id;
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+ uint64_t ptcr;
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+} PnvNMMU;
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+
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+#endif /*PPC_PNV_NMMU_H */
include/hw/ppc/pnv_xscom.h
+4
@@ -196,6 +196,10 @@ struct PnvXScomInterfaceClass {
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#define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300
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#define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100
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+#define PNV10_XSCOM_NEST0_MMU_BASE 0x2010c40
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+#define PNV10_XSCOM_NEST1_MMU_BASE 0x3010c40
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+#define PNV10_XSCOM_NMMU_SIZE 0x20
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+
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#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
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#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
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