target/riscv: Mask xepc[0] only when Zc* extension is enabled
IALIGN is 16 when the CPU supports the Zc* extension. Only xepc[0] should be masked when the Zc* extension is enabled. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260421074940.2916287-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang committed
Apr 21, 2026 at 15:49 UTC
b81ee019705a8d49aa4466fb51ddf8501df0c7f8
1 file changed
+9
-3
target/riscv/internals.h
+9
-3
@@ -173,9 +173,15 @@ static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)
173
174
static inline target_ulong get_xepc_mask(CPURISCVState *env)
175
{
176
- /* When IALIGN=32, both low bits must be zero.
177
- * When IALIGN=16 (has C extension), only bit 0 must be zero. */
178
- if (riscv_has_ext(env, RVC)) {
176
+ RISCVCPU *cpu = env_archcpu(env);
177
+
178
+ /*
179
+ * When IALIGN=32, both low bits must be zero.
180
+ * When IALIGN=16 (has C or Zc* extensions), only bit 0 must be zero.
181
+ */
182
+ if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca ||
183
+ cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce ||
184
+ cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) {
185
return ~(target_ulong)1;
186
} else {
187
return ~(target_ulong)3;