target/mips: add Octeon ZCB and ZCBT instructions
ZCB zeros the 128-byte cache block containing the base address. ZCBT has the same user-mode-visible memory effect for QEMU purposes. Model both forms with a single decodetree wildcard entry, align the address down to a 128-byte line, and store eight zero 128-bit chunks to guest memory. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-16-philmd@linaro.org>
James Hilliard committed
May 8, 2026 at 10:51 UTC
bb4caed97bb4b676a7a4c3e31e94077864f1316b
2 files changed
+28
target/mips/tcg/octeon.decode
+3
@@ -49,6 +49,9 @@ SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi
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SAA 011100 ..... ..... 00000 00000 011000 @saa
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SAAD 011100 ..... ..... 00000 00000 011001 @saa
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+&zcb base
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+ZCB 011100 base:5 00000 00000 1110- 011111 &zcb
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+
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&lx base index rd
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@lx ...... base:5 index:5 rd:5 ...... ..... &lx
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LWX 011111 ..... ..... ..... 00000 001010 @lx
target/mips/tcg/octeon_translate.c
+25
@@ -184,3 +184,28 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)
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TRANS(SAA, trans_saa, MO_32);
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TRANS(SAAD, trans_saa, MO_64);
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+
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+static bool trans_ZCB(DisasContext *ctx, arg_ZCB *a)
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+{
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+ TCGv_i64 addr = tcg_temp_new_i64();
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+ TCGv_i64 line = tcg_temp_new_i64();
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+ TCGv_i128 zero128 = tcg_zero_i128();
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+ const MemOp mop = mo_endian(ctx) | MO_128 | MO_ATOM_NONE;
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+
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+ gen_base_offset_addr(ctx, addr, a->base, 0);
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+
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+ /*
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+ * QEMU models ZCB/ZCBT as zeroing the containing 128-byte cache line
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+ * in guest memory.
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+ */
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+ tcg_gen_andi_i64(line, addr, ~0x7fULL);
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+
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+ for (int i = 0; i < 8; i++) {
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+ TCGv_i64 slot = tcg_temp_new_i64();
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+
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+ tcg_gen_addi_i64(slot, line, i * 16);
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+ tcg_gen_qemu_st_i128(zero128, slot, ctx->mem_idx, mop);
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+ }
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+
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+ return true;
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+}