linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses
Linux/MIPS enables software fixups for user-mode unaligned scalar accesses by default through MIPS_FIXADE/TIF_FIXADE. QEMU linux-user did not model that ABI, so MIPS guests took fatal AdEL/AdES exceptions unless translation was forced to use unaligned host accesses. Key MIPS translation blocks on the linux-user unaligned policy, implement sysmips(MIPS_FIXADE) to toggle that policy, and raise SIGBUS/BUS_ADRALN when fixups are disabled. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-4-philmd@linaro.org>
James Hilliard committed
Apr 8, 2026 at 20:54 UTC
bd8820aa7b0b8c03441feeaa790047f6028dbc38
7 files changed
+32
-3
linux-user/mips/cpu_loop.c
+5
@@ -161,6 +161,11 @@ done_syscall:
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case EXCP_DSPDIS:
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force_sig(TARGET_SIGILL);
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break;
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+ case EXCP_AdEL:
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+ case EXCP_AdES:
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+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
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+ env->CP0_BadVAddr);
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+ break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
linux-user/mips/target_syscall.h
+1
@@ -11,6 +11,7 @@
11
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#define TARGET_FORCE_SHMLBA
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#define TARGET_SYSMIPS_FLUSH_CACHE 3
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+#define TARGET_SYSMIPS_FIXADE 7
15
#define TARGET_SYSMIPS_ATOMIC_SET 2001
16
17
static inline abi_ulong target_shmlba(CPUMIPSState *env)
linux-user/mips64/target_syscall.h
+1
@@ -11,6 +11,7 @@
11
12
#define TARGET_FORCE_SHMLBA
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#define TARGET_SYSMIPS_FLUSH_CACHE 3
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+#define TARGET_SYSMIPS_FIXADE 7
15
#define TARGET_SYSMIPS_ATOMIC_SET 2001
16
17
static inline abi_ulong target_shmlba(CPUMIPSState *env)
linux-user/syscall.c
+8
@@ -6663,9 +6663,17 @@ static abi_long do_sysmips_atomic_set(CPUArchState *env, abi_ulong addr,
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static abi_long do_sysmips(CPUArchState *env, abi_long cmd, abi_long arg1,
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abi_long arg2)
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{
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+ CPUState *cs = env_cpu(env);
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+
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switch (cmd) {
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case TARGET_SYSMIPS_ATOMIC_SET:
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return do_sysmips_atomic_set(env, arg1, arg2);
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+ case TARGET_SYSMIPS_FIXADE:
6672
+ if (arg1 & ~3) {
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+ return -TARGET_EINVAL;
6674
+ }
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+ cs->prctl_unalign_sigbus = !(arg1 & 1);
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+ return 0;
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case TARGET_SYSMIPS_FLUSH_CACHE:
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return 0;
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default:
target/mips/cpu.c
+8
-2
@@ -560,11 +560,17 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
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static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs)
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{
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CPUMIPSState *env = cpu_env(cs);
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+ uint32_t flags = env->hflags & MIPS_HFLAG_TB_MASK;
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+
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+#ifdef CONFIG_USER_ONLY
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+ if (!cs->prctl_unalign_sigbus) {
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+ flags |= TB_FLAG_MIPS_FIXADE;
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+ }
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+#endif
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return (TCGTBCPUState){
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.pc = env->active_tc.PC,
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- .flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
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- MIPS_HFLAG_HWRENA_ULR),
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+ .flags = flags,
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};
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}
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target/mips/cpu.h
+4
@@ -1161,6 +1161,10 @@ typedef struct CPUArchState {
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#define MIPS_HFLAG_ELPA 0x4000000
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#define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
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#define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
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+#define MIPS_HFLAG_TB_MASK (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | \
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+ MIPS_HFLAG_HWRENA_ULR)
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+
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+#define TB_FLAG_MIPS_FIXADE 0x40000000
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target_ulong btarget; /* Jump / branch target */
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target_ulong bcond; /* Branch condition (if needed) */
1170
target/mips/tcg/translate.c
+5
-1
@@ -15070,6 +15070,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
15070
{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUMIPSState *env = cpu_env(cs);
15073
+ uint32_t tb_flags = ctx->base.tb->flags;
15074
15075
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
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ctx->saved_pc = -1;
@@ -15092,7 +15093,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
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ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
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/* Restore delay slot state from the tb context. */
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- ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
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+ ctx->hflags = tb_flags & MIPS_HFLAG_TB_MASK;
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ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
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ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
15099
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
@@ -15112,6 +15113,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
15114
(ctx->insn_flags & (ISA_MIPS_R6 |
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INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
15116
+ if (tb_flags & TB_FLAG_MIPS_FIXADE) {
15117
+ ctx->default_tcg_memop_mask = MO_UNALN;
15118
+ }
15119
15120
/*
15121
* Execute a branch and its delay slot as a single instruction.