target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release
All callers of gen_load_acquire() and gen_store_release() set both the MO_ALIGN|MO_TE flags. Set them once in each callee. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20260318103122.97244-7-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philippe Mathieu-Daudé committed
Mar 18, 2026 at 11:31 UTC
bf87f60b76d9d84b020adf38a83621db06a7559b
1 file changed
+10
-8
target/riscv/insn_trans/trans_rvzalasr.c.inc
+10
-8
@@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
29
return false;
30
}
31
32
+ memop |= MO_ALIGN | MO_TE;
33
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
34
35
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
@@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)
44
static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)
45
{
46
REQUIRE_ZALASR(ctx);
46
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));
47
+ return gen_load_acquire(ctx, a, MO_SB);
48
}
49
50
static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)
51
{
52
REQUIRE_ZALASR(ctx);
52
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
53
+ return gen_load_acquire(ctx, a, MO_SW);
54
}
55
56
static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)
57
{
58
REQUIRE_ZALASR(ctx);
58
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
59
+ return gen_load_acquire(ctx, a, MO_SL);
60
}
61
62
static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)
63
{
64
REQUIRE_64BIT(ctx);
65
REQUIRE_ZALASR(ctx);
65
- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
66
+ return gen_load_acquire(ctx, a, MO_UQ);
67
}
68
69
static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
@@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
79
return false;
80
}
81
82
+ memop |= MO_ALIGN | MO_TE;
83
memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;
84
85
/* Add a memory barrier implied by RL (mandatory) and AQ (optional) */
@@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)
92
static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)
93
{
94
REQUIRE_ZALASR(ctx);
93
- return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));
95
+ return gen_store_release(ctx, a, MO_SB);
96
}
97
98
static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)
99
{
100
REQUIRE_ZALASR(ctx);
99
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));
101
+ return gen_store_release(ctx, a, MO_SW);
102
}
103
104
static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)
105
{
106
REQUIRE_ZALASR(ctx);
105
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));
107
+ return gen_store_release(ctx, a, MO_SL);
108
}
109
110
static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)
111
{
112
REQUIRE_64BIT(ctx);
113
REQUIRE_ZALASR(ctx);
112
- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));
114
+ return gen_store_release(ctx, a, MO_UQ);
115
}