target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f
The risc-v vector spec defines vmv.s.x and vfmv.s.f as writing element 0 of the destination register while the remaining destination elements follow the current tail policy. When QEMU runs with rvv_ta_all_1s enabled, those elements must therefore become all 1s. QEMU handled both instructions as translation-time special cases that directly wrote vd[0] and skipped the usual tail processing. As a result, vmv.s.x and vfmv.s.f left the remaining destination elements unchanged instead of applying the configured tail policy. Fix this by routing both instructions through a helper that writes vd[0] and then treats the rest of the destination register as tail, reusing the existing agnostic-element fill logic. Signed-off-by: Zhongyao Chen <chen.zhongyao@zte.com.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <202605061005.646A537u037157@mse-fl1.zte.com.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
chen.zhongyao@zte.com.cn committed
May 6, 2026 at 15:16 UTC
c24f58d5322b7eedce6bc38348d36a4d44c58bf8
3 files changed
+36
-30
target/riscv/helper.h
+4
@@ -662,6 +662,10 @@ DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32)
662
DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32)
663
DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32)
664
DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32)
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+DEF_HELPER_4(vset_velem0_b, void, ptr, i64, env, i32)
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+DEF_HELPER_4(vset_velem0_h, void, ptr, i64, env, i32)
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+DEF_HELPER_4(vset_velem0_w, void, ptr, i64, env, i32)
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+DEF_HELPER_4(vset_velem0_d, void, ptr, i64, env, i32)
669
670
DEF_HELPER_6(vsaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
671
DEF_HELPER_6(vsaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
target/riscv/insn_trans/trans_rvv.c.inc
+14
-30
@@ -3607,37 +3607,21 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
3607
load_element(dest, tcg_env, endian_ofs(s, vreg, idx), s->sew, sign);
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}
3609
3610
-/* Integer Scalar Move Instruction */
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+typedef void gen_helper_vset_velem0(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
3611
3612
-static void store_element(TCGv_i64 val, TCGv_ptr base,
3613
- int ofs, int sew)
3612
+static void vec_element_storei_tail(DisasContext *s, int vreg, TCGv_i64 val)
3613
{
3615
- switch (sew) {
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- case MO_8:
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- tcg_gen_st8_i64(val, base, ofs);
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- break;
3619
- case MO_16:
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- tcg_gen_st16_i64(val, base, ofs);
3621
- break;
3622
- case MO_32:
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- tcg_gen_st32_i64(val, base, ofs);
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- break;
3625
- case MO_64:
3626
- tcg_gen_st_i64(val, base, ofs);
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- break;
3628
- default:
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- g_assert_not_reached();
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- }
3631
-}
3614
+ static gen_helper_vset_velem0 * const fns[4] = {
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+ gen_helper_vset_velem0_b, gen_helper_vset_velem0_h,
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+ gen_helper_vset_velem0_w, gen_helper_vset_velem0_d,
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+ };
3618
+ TCGv_ptr dest = tcg_temp_new_ptr();
3619
+ uint32_t data = FIELD_DP32(0, VDATA, VTA, s->vta);
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+ TCGv_i32 desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb,
3621
+ s->cfg_ptr->vlenb, data));
3622
3633
-/*
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- * Store vreg[idx] = val.
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- * The index must be in range of VLMAX.
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- */
3637
-static void vec_element_storei(DisasContext *s, int vreg,
3638
- int idx, TCGv_i64 val)
3639
-{
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- store_element(val, tcg_env, endian_ofs(s, vreg, idx), s->sew);
3623
+ tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vreg));
3624
+ fns[s->sew](dest, val, tcg_env, desc);
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}
3626
3627
/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
@@ -3684,7 +3668,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
3668
*/
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s1 = get_gpr(s, a->rs1, EXT_NONE);
3670
tcg_gen_ext_tl_i64(t1, s1);
3687
- vec_element_storei(s, a->rd, 0, t1);
3671
+ vec_element_storei_tail(s, a->rd, t1);
3672
gen_set_label(over);
3673
tcg_gen_movi_tl(cpu_vstart, 0);
3674
finalize_rvv_inst(s);
@@ -3741,7 +3725,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
3725
t1 = tcg_temp_new_i64();
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do_nanbox(s, t1, cpu_fpr[a->rs1]);
3727
3744
- vec_element_storei(s, a->rd, 0, t1);
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+ vec_element_storei_tail(s, a->rd, t1);
3729
3730
gen_set_label(over);
3731
tcg_gen_movi_tl(cpu_vstart, 0);
target/riscv/vector_helper.c
+18
@@ -2141,6 +2141,24 @@ GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2)
2141
GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4)
2142
GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8)
2143
2144
+#define GEN_VEXT_SET_VELEM0(NAME, ETYPE, H) \
2145
+void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
2146
+ uint32_t desc) \
2147
+{ \
2148
+ uint32_t esz = sizeof(ETYPE); \
2149
+ uint32_t vlenb = riscv_cpu_cfg(env)->vlenb; \
2150
+ uint32_t vta = vext_vta(desc); \
2151
+ \
2152
+ *((ETYPE *)vd + H(0)) = (ETYPE)s1; \
2153
+ /* Treat every element past vd[0] as tail for scalar-to-vector moves. */ \
2154
+ vext_set_elems_1s(vd, vta, esz, vlenb); \
2155
+}
2156
+
2157
+GEN_VEXT_SET_VELEM0(vset_velem0_b, int8_t, H1)
2158
+GEN_VEXT_SET_VELEM0(vset_velem0_h, int16_t, H2)
2159
+GEN_VEXT_SET_VELEM0(vset_velem0_w, int32_t, H4)
2160
+GEN_VEXT_SET_VELEM0(vset_velem0_d, int64_t, H8)
2161
+
2162
#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H) \
2163
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
2164
CPURISCVState *env, uint32_t desc) \