target/mips: add Octeon SAAD instruction
SAAD is the doubleword form of SAA: it atomically adds rt to the naturally aligned 64-bit doubleword at base and discards the old memory value. Route it through the common SAA/SAAD translator so the MemOp selects the aligned doubleword transaction size. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20260520172313.23777-15-philmd@linaro.org>
James Hilliard committed
May 8, 2026 at 10:51 UTC
c3d9cbb789f8beabcf1239d73b7fd9b5a1fbb2cd
2 files changed
+2
target/mips/tcg/octeon.decode
+1
@@ -47,6 +47,7 @@ SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi
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&saa base rt
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@saa ...... base:5 rt:5 ................ &saa
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SAA 011100 ..... ..... 00000 00000 011000 @saa
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+SAAD 011100 ..... ..... 00000 00000 011001 @saa
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&lx base index rd
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@lx ...... base:5 index:5 rd:5 ...... ..... &lx
target/mips/tcg/octeon_translate.c
+1
@@ -183,3 +183,4 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)
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}
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TRANS(SAA, trans_saa, MO_32);
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+TRANS(SAAD, trans_saa, MO_64);