target/arm: migrate Granule Protection traps to registerfields
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20260422125250.1303100-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée committed
Apr 22, 2026 at 13:52 UTC
cd28d3e7967993a8e6f2e81caf5669ac404c833b
1 file changed
+27
-3
target/arm/syndrome.h
+27
-3
@@ -462,12 +462,36 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
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return res;
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}
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+/*
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+ * ISS encoding for a Granule Protection Check exception
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+ *
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+ * These are only reported to EL3
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+ */
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+FIELD(GPC_ISS, xFSC, 0, 6)
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+FIELD(GPC_ISS, WnR, 6, 1) /* Write not Read */
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+FIELD(GPC_ISS, S1PTW, 7, 1)
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+FIELD(GPC_ISS, CM, 8, 1)
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+FIELD(GPC_ISS, VNCR, 13, 1)
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+FIELD(GPC_ISS, GPCSC, 14, 6)
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+FIELD(GPC_ISS, InD, 20, 1) /* Instruction not Data access */
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+FIELD(GPC_ISS, S2PTW, 21, 1)
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+
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static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,
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int cm, int s1ptw, int wnr, int fsc)
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{
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- return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21)
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- | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8)
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- | (s1ptw << 7) | (wnr << 6) | fsc;
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+ uint32_t res = syn_set_ec(0, EC_GPC);
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+ res = FIELD_DP32(res, SYNDROME, IL, 1);
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+
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+ res = FIELD_DP32(res, GPC_ISS, S2PTW, s2ptw);
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+ res = FIELD_DP32(res, GPC_ISS, InD, ind);
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+ res = FIELD_DP32(res, GPC_ISS, GPCSC, gpcsc);
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+ res = FIELD_DP32(res, GPC_ISS, VNCR, vncr);
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+ res = FIELD_DP32(res, GPC_ISS, CM, cm);
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+ res = FIELD_DP32(res, GPC_ISS, S1PTW, s1ptw);
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+ res = FIELD_DP32(res, GPC_ISS, WnR, wnr);
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+ res = FIELD_DP32(res, GPC_ISS, xFSC, fsc);
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+
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+ return res;
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}
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static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)