target/loongarch: Replace legacy ldq_le_phys() -> address_space_ldq_le()
Prefer the address_space_ld/st API over the legacy ld/st_phys() because it allow checking for bus access fault (although the modified code doesn't check that). There is no logical change. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20260319104944.66690-2-philmd@linaro.org>
Philippe Mathieu-Daudé committed
Mar 18, 2026 at 14:54 UTC
d14617e561ae2e3cc5b42ae623fb18767e7aefc3
2 files changed
+16
-7
target/loongarch/cpu_helper.c
+9
-4
@@ -7,6 +7,7 @@
7
*/
8
9
#include "qemu/osdep.h"
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+#include "system/memory.h"
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#include "system/tcg.h"
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#include "cpu.h"
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#include "accel/tcg/cpu-mmu-index.h"
@@ -145,6 +146,7 @@ static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys,
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TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
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int access_type, int mmu_idx, int debug)
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{
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+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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CPUState *cs = env_cpu(env);
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hwaddr index = 0, phys = 0;
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uint64_t palen_mask = loongarch_palen_mask(env);
@@ -174,7 +176,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
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/* get next level page directory */
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index = (address >> dir_base) & ((1 << dir_width) - 1);
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phys = base | index << 3;
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- base = ldq_le_phys(cs->as, phys);
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+ base = address_space_ldq_le(cs->as, phys, attrs, NULL);
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if (level) {
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if (FIELD_EX64(base, TLBENTRY, HUGE)) {
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/* base is a huge pte */
@@ -204,10 +206,13 @@ restart:
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context->pte_buddy[1 - index] = base + BIT_ULL(dir_base);
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base += (BIT_ULL(dir_base) & address);
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} else if (cpu_has_ptw(env)) {
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+ uint64_t val;
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+
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index &= 1;
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context->pte_buddy[index] = base;
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- context->pte_buddy[1 - index] = ldq_le_phys(cs->as,
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- phys + 8 * (1 - 2 * index));
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+ val = address_space_ldq_le(cs->as, phys + 8 * (1 - 2 * index),
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+ attrs, NULL);
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+ context->pte_buddy[1 - index] = val;
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}
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context->ps = dir_base;
@@ -239,7 +244,7 @@ restart:
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ret1 = loongarch_cmpxchg_phys(cs, phys, pte, base);
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/* PTE updated by other CPU, reload PTE entry */
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if (ret1 == MEMTX_DECODE_ERROR) {
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- base = ldq_le_phys(cs->as, phys);
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+ base = address_space_ldq_le(cs->as, phys, attrs, NULL);
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goto restart;
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}
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target/loongarch/tcg/tlb_helper.c
+7
-3
@@ -20,6 +20,7 @@
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#include "exec/log.h"
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#include "cpu-csr.h"
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#include "tcg/tcg_loongarch.h"
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+#include "system/memory.h"
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typedef bool (*tlb_match)(bool global, int asid, int tlb_asid);
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@@ -709,7 +710,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
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hwaddr index, phys;
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uint64_t palen_mask = loongarch_palen_mask(env);
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uint64_t dir_base, dir_width;
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-
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+ uint64_t val;
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if (unlikely((level == 0) || (level > 4))) {
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qemu_log_mask(LOG_GUEST_ERROR,
@@ -736,7 +737,9 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
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get_dir_base_width(env, &dir_base, &dir_width, level);
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index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
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phys = base | index << 3;
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- return ldq_le_phys(cs->as, phys) & palen_mask;
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+ val = address_space_ldq_le(cs->as, phys, MEMTXATTRS_UNSPECIFIED, NULL);
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+
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+ return val & palen_mask;
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}
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void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
@@ -802,7 +805,8 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
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ptoffset0 = ptindex << 3;
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ptoffset1 = (ptindex + 1) << 3;
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phys = base | (odd ? ptoffset1 : ptoffset0);
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- pte_raw = ldq_le_phys(cs->as, phys);
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+ pte_raw = address_space_ldq_le(cs->as, phys,
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+ MEMTXATTRS_UNSPECIFIED, NULL);
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tmp0 = loongarch_sanitize_hw_pte(env, pte_raw);
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ps = ptbase;
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}