hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR
The IRS_SYNCR register is used by software to request synchronization of interrupt events. This means that in-flight interrupt events are guaranteed to have been delivered. Since QEMU's implementation is entirely synchronous, syncs are a no-op for us. This means we can ignore writes to IRS_SYNCR and always report "sync complete" via the IDLE bit in IRS_SYNC_STATUSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-31-peter.maydell@linaro.org
Peter Maydell committed
Mar 27, 2026 at 11:16 UTC
d304e788c667a49522c080d5dda2ec182037e39c
1 file changed
+7
hw/intc/arm_gicv5.c
+7
@@ -1087,6 +1087,10 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
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case A_IRS_CR1:
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*data = cs->irs_cr1[domain];
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return true;
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+ case A_IRS_SYNC_STATUSR:
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+ /* Sync is a no-op for QEMU: we are always IDLE */
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+ *data = R_IRS_SYNC_STATUSR_IDLE_MASK;
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+ return true;
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}
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return false;
@@ -1172,6 +1176,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,
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case A_IRS_CR1:
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cs->irs_cr1[domain] = data;
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return true;
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+ case A_IRS_SYNCR:
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+ /* Sync is a no-op for QEMU: ignore write */
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+ return true;
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}
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return false;