@samitouri / QOSamiQemu / commits / d735016e91

target/loongarch: Add support for dbar hint variants

LoongArch architecture (since LA664) introduces fine-grained dbar hints that allow controlling which memory accesses are ordered by the barrier. Previously, all dbar instructions were treated as a full barrier (TCG_MO_ALL | TCG_BAR_SC). This patch adds support for decoding dbar hints and emitting the appropriate TCG memory barrier flags. For CPUs that do not advertise the DBAR_HINTS feature (cpucfg3.DBAR_HINTS = 0), all dbar hints fall back to a full barrier, preserving compatibility. The hint encoding follows the LoongArch v1.10 specification: The hint is a 5-bit field (bits 4-0). Bit4 is reserved and currently ignored/discarded. Only bits 3-0 are used for ordering control. * Bit3: barrier for previous read (0: true, 1: false) * Bit2: barrier for previous write (0: true, 1: false) * Bit1: barrier for succeeding read (0: true, 1: false) * Bit0: barrier for succeeding write (0: true, 1: false) The mapping to TCG memory order flags is as follows: TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST; TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST; TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD; TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST; Special hint handling: - hint 0x700: LL/SC loop barrier, treated as a full barrier as recommended. - hint 0xf and 0x1f: reserved/no-op, treated as no operation Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>

Song Gao committed Apr 16, 2026 at 19:47 UTC d735016e9111e7bf0c2457556cedafd387c044a9
4 files changed +69 -2
target/loongarch/cpu.c
+4
@@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj)
455 data = FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1);
456 data = FIELD_DP32(data, CPUCFG2, SCQ, 1);
457 cpu->env.cpucfg[2] = data;
458 +
459 + data = cpu->env.cpucfg[3];
460 + data = FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1);
461 + cpu->env.cpucfg[3] = data;
462 }
463 }
464
target/loongarch/tcg/insn_trans/trans_memory.c.inc
+61 -2
@@ -137,11 +137,70 @@ static bool trans_preldx(DisasContext *ctx, arg_preldx * a)
137 return true;
138 }
139
140 +/*
141 + * Decode dbar hint and emit appropriate TCG memory barrier.
142 + *
143 + * The hint is a 5-bit field (0-31) encoded in the instruction.
144 + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier.
145 + *
146 + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details.
147 + */
148 static bool trans_dbar(DisasContext *ctx, arg_dbar * a)
149 {
142 - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
150 + int hint = a->imm;
151 + TCGBar bar_flags = 0;
152 +
153 + /* Reserved/no-op hints: 0xf and 0x1f */
154 + if (hint == 0xf || hint == 0x1f) {
155 + return true;
156 + }
157 +
158 + /* If the CPU does not support fine-grained hints,or for the special LL/SC
159 + * loop barrier (0x700), emit a full barrier.
160 + */
161 + if (!avail_DBAR_HINT(ctx) || hint == 0x700) {
162 + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
163 + return true;
164 + }
165 +
166 + /*
167 + * Fine-grained hint decoding:
168 + * The hint is a 5-bit field (bits 4-0). Bit4 is reserved and currently
169 + * ignored/discarded. Only bits 3-0 are used for ordering control.
170 + * Bit3: barrier for previous read (0: true, 1: false)
171 + * Bit2: barrier for previous write (0: true, 1: false)
172 + * Bit1: barrier for succeeding read (0: true, 1: false)
173 + * Bit0: barrier for succeeding write (0: true, 1: false)
174 + *
175 + * For each combination, we set the corresponding TCG_MO_* flag if both
176 + * sides of the barrier require ordering.
177 + */
178 +
179 + bool prev_rd = !(hint & 0x08); /* bit3 */
180 + bool prev_wr = !(hint & 0x04); /* bit2 */
181 + bool succ_rd = !(hint & 0x02); /* bit1 */
182 + bool succ_wr = !(hint & 0x01); /* bit0 */
183 +
184 + if (prev_rd) {
185 + bar_flags |= TCG_MO_LD_LD | TCG_MO_LD_ST;
186 + }
187 + if (prev_wr) {
188 + bar_flags |= TCG_MO_ST_LD | TCG_MO_ST_ST;
189 + }
190 + if (succ_rd) {
191 + bar_flags |= TCG_MO_LD_LD | TCG_MO_ST_LD;
192 + }
193 + if (succ_wr) {
194 + bar_flags |= TCG_MO_ST_ST | TCG_MO_LD_ST;
195 + }
196 +
197 + if (bar_flags == 0) {
198 + bar_flags = TCG_MO_ALL;
199 + }
200 +
201 + tcg_gen_mb(bar_flags | TCG_BAR_SC);
202 return true;
144 -}
203 + }
204
205 static bool trans_ibar(DisasContext *ctx, arg_ibar *a)
206 {
target/loongarch/tcg/translate.c
+1
@@ -149,6 +149,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
149
150 ctx->cpucfg1 = env->cpucfg[1];
151 ctx->cpucfg2 = env->cpucfg[2];
152 + ctx->cpucfg3 = env->cpucfg[3];
153 }
154
155 static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
target/loongarch/translate.h
+3
@@ -43,6 +43,8 @@
43 #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))
44 #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))
45
46 +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS))
47 +
48 /*
49 * If an operation is being performed on less than TARGET_LONG_BITS,
50 * it may require the inputs to be sign- or zero-extended; which will
@@ -66,6 +68,7 @@ typedef struct DisasContext {
68 bool va32; /* 32-bit virtual address */
69 uint32_t cpucfg1;
70 uint32_t cpucfg2;
71 + uint32_t cpucfg3;
72 } DisasContext;
73
74 void generate_exception(DisasContext *ctx, int excp);