@samitouri / QOSamiQemu / commits / dc634aa347

target/riscv: tt-ascalon: Add Tenstorrent mvendorid

JEP106 has two vendor IDs for Tenstorrent. We will use Bank 16, company 33: ((16 - 1) << 7) | 33 = 0x7a1 As JEP106 requires registration to download, the number can confirmed by looking at the OpenOCD sources[1]. Alternatively, referring to the JEDEC document the hex IDs are listed with the parity (MSB) bit added. Company 33 has hex 0xa1: ((16 - 1) << 7) | (0xa1 & ~0x80) = 0x7a1 Add it to the Ascalon CPU definition as the mvendorid CSR. [1] https://github.com/openocd-org/openocd/blob/1ebff3ab33c77e3f8fb4e1ddda262b606b572af1/src/helper/jep106.inc#L1935 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Michael Ellerman <mpe@oss.tenstorrent.com> Message-ID: <20260114020516.982305-1-joel@jms.id.au> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

Joel Stanley committed Jan 14, 2026 at 12:35 UTC dc634aa347abcdbd9eca54d2a6c93f5b1b200ff6

2 files changed +4

target/riscv/cpu.c

@@ -3207,6 +3207,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {

3207 .cfg.ext_svnapot = true,

3208 .cfg.ext_svpbmt = true,

3209

3210 + .cfg.mvendorid = TENSTORRENT_VENDOR_ID,

3211 +

3212 .cfg.max_satp_mode = VM_1_10_SV57,

3213 ),

3214

target/riscv/cpu_vendorid.h

@@ -8,4 +8,6 @@

8 #define VEYRON_V1_MIMPID 0x111

9 #define VEYRON_V1_MVENDORID 0x61f

11 +#define TENSTORRENT_VENDOR_ID 0x7a1

12 +

13 #endif /* TARGET_RISCV_CPU_VENDORID_H */